Question

我写了上/下计数器并为可设置的起点创建了代码。到目前为止这么好，但我想不出如何将它添加到柜台。我必须强调一点，我对Verilog和类似的语言都是新手。

//UTILS

reg  [2:0] delay;
wire clock;


reg[3:0] tens;
reg[3:0] units;


wire[5:0] number; 
reg[13:0] shift;    
integer i;


//ASSIGNS
assign number[5:0] = SW[5:0];
assign up = SW[7];
assign start = SW[6];



//PRESCALER
always@ (posedge MCLK)
 begin
    delay <= delay + 1;
 end

assign clock = &delay;


//MAIN COUNTER 
always@ (posedge clock)
begin
     if (start)
        begin
            if (up) //going up
                begin
                    if (units == 4'd3 && tens == 4'd6)
                        begin       //63 reached
                            units <= 0;
                            tens <=0;
                        end
                    if (units==4'd9) 
                       begin        //x9 reached                
                            units <= 0;
                            tens <= tens + 1;
                       end
                    else
                        units <= units + 1; //typical case
                end
            else    //goin down
                begin
                    if (units == 4'd0)      
                        if ( tens ==4'd0)   //00 reached back to 63
                            begin
                                units <= 4'd3;
                                tens <= 4'd6;
                            end
                        else
                            begin           //x0 reached
                                tens <= tens-1;
                                units <= 4'd9;
                            end
                    else
                        begin               //typical case
                            units <= units -1;
                        end
                end
        end 
end             //MAIN COUNTER END

在这里我不知道如何合并这两件，我很想拥有它如果开始总是@ posedge时钟 / 计数 / 其他 / *几乎在功能上改变数字（当发生变化时立即改变）* /

将其添加到 if（start）else 似乎可以完成工作，但仅限于相当低频时钟的上升沿。据我所知，我不能在两个不同的ALWAYS @中使用一个reg。

 /* // Clear previous number and store new number in shift register
          shift[13:6] = 0;
          shift[5:0] = number;

          //BINARY TO BCD                               
          for (i=0; i<6; i=i+1) 
            begin
                 if (shift[9:6] >= 5)
                    shift[9:6] = shift[9:6] + 3;

                 if (shift[13:10] >= 5)
                    shift[13:10] = shift[13:10] + 3;
                 shift = shift << 1; 
            end
        units <=  shift[9:6];
        tens <= shift[13:10];

*/

dek7seg是7段显示，100％罚款（教授的代码）。

dek7seg ss1(
 .bits(units[3:0]),
 .seg(DISP1[6:0])
);

dek7seg ss10(
 .bits(tens[3:0]),
 .seg(DISP2[6:0])
);



endmodule

Answer 1

您正在使用派生时钟来控制 MAIN COUNTER 。而是使用主时钟MCLK并使用delay的逻辑作为条件语句。

由于您希望在number的更改中存储新值，因此您需要存储之前的number值并进行比较。

根据您的描述，您的代码应如下所示：

//MAIN COUNTER 
always@ (posedge MCLK)
begin
  if (start && &delay)
  begin
      /* your up/down logic here */
  end
  else if (number != prev_number)
  begin // Clear previous number and store new number
    prev_number <= number;
    units <= new_units;
    tens  <= new_tens;
  end
end

// Calculate new units and tens from number
always @* begin
  shift[13:6] = 0;
  shift[5:0] = number;

  //BINARY TO BCD                               
  for (i=0; i<6; i=i+1) begin
    if (shift[9:6] >= 5)
      shift[9:6] = shift[9:6] + 3;

    if (shift[13:10] >= 5)
      shift[13:10] = shift[13:10] + 3;

    shift = shift << 1; 
  end

  new_units = shift[9:6];
  new_tens  = shift[13:10];
end

在Verilog计数器中无法适应可设置性

1 个答案: