Question

我正在尝试使用verilog在我的baysis2 FGPA上创建一个简单的4位数密码系统。我想使用7段显示来显示输入的数字（它们将使用键盘输入）。现在我只是测试以确保在输入时显示正确的数字。问题是，七段显示的第一个数字在所有其他数据显示时都不会亮起。我已经在多个电路板上尝试过它，并且所有其他数字都可以通过相同的电线启用。为什么会这样？

NET "seven_seg_display[6]" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seven_seg_display[5]" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seven_seg_display[4]" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seven_seg_display[3]" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seven_seg_display[2]" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seven_seg_display[1]" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seven_seg_display[0]" LOC = "M12"; # Bank = 1, Signal name = CG
#NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP

NET "assert_seg" LOC = "K14"; # Bank = 1, Signal name = AN3
NET "assert_seg" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "assert_seg" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "assert_seg" LOC = "F12"; # Bank = 1, Signal name = AN0

UCF

static func postData (url: String,token: String,params :Dictionary<String,AnyObject>){
        print("POSTINGGGGGG")
        Alamofire.request(.POST, url, parameters: params,headers: ["X-Authorization": token])
            .responseJSON { response in
                switch response.result {
                case .Success(let data): break
                    //let resultJSON = JSON(data).dictionaryValue
                   // print(data)
                case .Failure(let error):
                    print(error)
                }
        }
    }

Answer 1

问题是，七段显示器的第一个数字在所有其他段显示时都没有亮起。

我假设您的七段显示中有两位数字，因此您需要从14-bit seven_seg_display模块获得enter_password的输出

更改

    output wire [6:0]  seven_seg_display,

到

    output wire [13:0]  seven_seg_display,

您还可能需要更改以下代码的逻辑，以支持14-bit seven_seg_display和多路复用器，以确定seven_seg_display的哪一半将被ascii_code分配：< / p>

    assign seven_seg_display =  
       ascii_code == 8'h30 ? 7'b0000001: //0
       ascii_code == 8'h31 ? 7'b1001111: //1
       ascii_code == 8'h32 ? 7'b0010010: //2
       ascii_code == 8'h33 ? 7'b0000110: //3
       ascii_code == 8'h34 ? 7'b1001100: //4
       ascii_code == 8'h35 ? 7'b0100100: //5
       ascii_code == 8'h36 ? 7'b0100000: //6
       ascii_code == 8'h37 ? 7'b0001111: //7
       ascii_code == 8'h38 ? 7'b0000000: //8
       ascii_code == 8'h39 ? 7'b0000100: //9
                             7'b1111111; //e for error 0

Baysis2 Verilog - 7段显示的第一个数字不会工作

1 个答案: