Question

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DruigZadatak is
 Port ( iSW : in  STD_LOGIC_VECTOR (7 downto 0);
       iSEL : in  STD_LOGIC;
       oLED : out  STD_LOGIC_VECTOR (7 downto 0));
 end DruigZadatak;

 architecture Behavioral of DruigZadatak is

begin
    oLED <= "11111111" when iSEL ='0' else
            oLED(3 downto 0) <= (iSW(5 downto 3) + iSW(2 downto 0)),
            oLED(6 downto 4) <= "111" when iSW(7)='1' else
            "110" when iSW(6)='1' else
            "101" when iSW(5)='1' else
            "100" when iSW(4)='1' else
            "011" when iSW(3)='1' else
            "010" when iSW(2)='1' else
            "001" when iSW(1)='1' else  
            "000" when iSW(0)='1';  
    oLed(7) <= '0' when iSW ="00000000" else
        iSEL;
 end Behavioral;

我得到以下错误

ERROR:HDLCompiler:288 -Line 45: Cannot read from 'out' object oled ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 -Line 45: found '0' definitions of operator "<=", cannot determine exact overloaded matching  definition for "<="
ERROR:HDLCompiler:288 -Line 47: Cannot read from 'out' object oled ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 -Line 47: found '0'   definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:854 -Line 39: Unit <behavioral> ignored due to previous errors.

如果有人可以向我解释我该怎么做以及为什么这些错误不断出现它会很棒，谢谢。我希望你明白我的项目有什么意义..

Answer 1

您的条件信号赋值语句不能嵌入其他条件信号赋值语句。

将作业分成三部分而不是两部分：

 architecture foo of DruigZadatak is

 begin
     oLED (6 downto 4) <= "111" when iSEL = '0' or iSW(7) = '1' else 
                          "110" when iSW(6)='1' else
                          "101" when iSW(5)='1' else
                          "100" when iSW(4)='1' else
                          "011" when iSW(3)='1' else
                          "010" when iSW(2)='1' else
                          "001" when iSW(1)='1' else  
                          "000" when iSW(0)='1';                       

     oLED ( 3 downto 0) <= "1111"                    when iSEL = '0' else
                           '0' & (iSW(5 downto 3) + iSW(2 downto 0)) ;
     oLed(7) <= '0'   when iSW ="00000000" else    
                iSEL;                      
 end architecture;

还要注意“0”与加法结果的串联，使得右侧表达式长度与赋值的左侧相匹配。

这三个作业用if语句详细说明为等效过程。您可以将if语句组合到一个进程中，它们都具有相同的敏感性列表。

使用符合VHDL -2008标准的工具，您可以在一个过程中使用顺序条件信号赋值语句。

以上架构有三个并发信号赋值语句进行分析，阐述和模拟（告诉我们没有长度不匹配，一切都连接起来）。

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