Question

获取错误9: error: genvar is missing for generate "loop" variable 'r'. 1 error(s) during elaboration.

整个代码：

module divider (dividend, divisor, quotient, remainder ) ;
    input [7:0] dividend ; // eight input lines modeled as a bus
    input [7:0] divisor ; // select lines bundled as a bus
    output reg [7:0] quotient ;
    output reg [7:0] remainder ;
    reg [7:0] r;
    reg [7:0] q;
    assign q = 0;
    for(r = dividend; r >= divisor; r = r - divisor)
        assign q = q + 1;
    assign remainder = r;
    assign quotient = q;
endmodule

module main;
    reg [7:0] dd;
    assign dd = 12;
    reg [7:0] dr;
    assign dr = 5;
    reg [7:0] q;
    reg [7:0] r;
    wire a = divider(dd, dr, q, r);
    initial begin
    $display("quotient %d", q);
    $display("remainder %d",r);
    end
endmodule

我正在尝试编写一个模块，通过使用verilog中的行为建模重复减法来计算商和余数。这是我的第一个verilog程序，我在修复这些错误时遇到问题，请指出我的代码中是否还有其他错误。

Answer 1

问题在于for循环。您可以使用生成块或始终块来使用它。其中一种方法如下：

module divider (dividend, divisor,quotient, remainder ) ;
input [7:0] dividend ; // eight input lines modeled as a bus
input [7:0] divisor ; // select lines bundled as a bus

output reg [7:0] quotient ;
output reg[7:0] remainder ;

 always @(*) 
  begin
       quotient=0;
       for(remainder = dividend; remainder >= divisor; remainder = remainder - divisor)
          quotient = quotient + 1;            
  end

endmodule



module main;

reg[7:0] dd; 
reg[7:0] dr;

wire [7:0] q;
wire [7:0] r;

divider d0( .dividend(dd), .divisor(dr), .quotient(q), .remainder(r) ) ;

initial begin
   dd=12;
   dr=5;
end

initial begin
 #20  $display("quotient %d", q);
 #25    $display("remainder %d",r);
end

endmodule

很少有事情需要注意：

如果您想使用 assign 语句分配变量，请将该变量声明为 wire 。
在测试平台中，您需要将输入定义为＆＃34; reg＆＃34;输出为＆＃34; wire＆＃34;。
您不能在for循环中使用分配。

genvar缺少生成“循环”变量：verilog

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