Question

我需要构建一个计算器，它接受2个带符号的16位数字（in1，in2），并根据opCode（4位输入）对它们执行预处理功能。输出应该是一个带符号的16位数字，名为“结果”，一位是“溢出”

我真的需要帮助修复我的代码。它不起作用，我不确定我做错了什么。

操作码

0000 .....添加in1和in2
0001 .....减去in1-in2
0010 .....将in1除以10，其余为1或0（使用模数运算符）
0011 .....按位AND in1 in2
0100 .....按位xOR in1 | in2
0101 .....补充in1
0110 .....按位或in1 in2
0111 .....补充in1
1000 ..... in1 by 1

1001 ....减1 in1

module calculator(
    input [15:0] in1,
    input [15:0] in2,
    input [3:0] opCode,
    output [15:0]
    );
    reg [3:0] opCode;
    reg [15:0] in1;
    reg [15:0] in2;
    reg [15:0] result;   
    reg overflow;


always @ (opcode) begin 
    if (opCode == 0000) begin // add in1+in2
        result=in1+in2; 
                      $display("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1, in2, result, overflow);
            $monitor("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1, in2, result, overflow);
     end
    if (opCode == 0001) begin   //subtract in1-in3
     result=in1-in2; 
            $display("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1, in2, result, overflow);
            $monitor("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1, in2, result, overflow);
             end


    if (opCode == 0011) begin   //divide int1 by 10 w/ remainder as overflow
     result=in1%10; 
            $display("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
            $monitor("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
             end


    if (opCode == 0100) begin   //preforms AND operation in1 in2
     result=in1&int2; 
            $display("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
            $monitor("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
             end


    if (opCode == 0101) begin   //preforms XOR operation in1 in2
     result=in1^int2; 
            $display("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
            $monitor("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
             end


    if (opCode == 0110) begin   //preforms OR op on in1 in 2
     result=in1|int2; 
            $display("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
            $monitor("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1,in2, result, overflow);
             end


    if (opCode == 0111) begin   //complement of in1
     result=!in1; 
            $display("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
            $monitor("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
             end


    if (opCode == 1001) begin   //increase in1 by 1
     result=in1+1; 
            $display("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
            $monitor("opCode(%b),in1(%d),result(%d),overflow(%b)", opCode, in1, result, overflow);
             end


    if (opCode == 1000) begin   //decrease in2 by 1
     result=in2-1; 
            $display("opCode(%b),in2(%d),result(%d),overflow(%b)", opCode, in2, result, overflow);
            $monitor("opCode(%b),in2(%d),result(%d),overflow(%b)", opCode, in2, result, overflow);
             end


end
 end
 endmodule


 endmodule

Answer 1

我强调了几个问题：

module calculator(
  input [15:0] in1, //<-- title says inputs are signed
  input [15:0] in2,
  input [3:0] opCode,
  output [15:0] //<-- undeclared name
);
reg [3:0] opCode;
reg [15:0] in1; //<-- inputs can not be reg
reg [15:0] in2;
reg [15:0] result;   
reg overflow;

应该是：

module calculator(
  input      signed [15:0] in1,
  input      signed [15:0] in2,
  input              [3:0] opCode,
  output reg signed [15:0] result
);  
reg overflow;

Verilog Calculator具有16位带符号输入

1 个答案: