我是VHDL的新手,我试图创建一个从输入接收值并计数到给定值然后输出1的计数器;
例如,输入是一个4位向量" 1011"我试图设置一个整数信号a = input = 1011 = 11十进制,然后如果b = a = 11输出1,否则输出0和b = b + 1
我知道我可以通过一系列if语句来实现它,但我想知道是否有更好的方法,比如将值直接从输入向量分配给整数信号?感谢任何可以提供帮助的人!
答案 0 :(得分:1)
这是未经测试的,但它听起来像是你之后的一般架构。在VHDL中使用if
语句是不错的做法;他们需要定义顺序(非组合)逻辑;你只需要明智地使用它们。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Counter is port (
enable: in std_logic; -- Used to increment the counter. (Active high.)
value: in std_logic_vector(0 to 3);
clk: in std_logic; -- Used to clock the counter.
reset: in std_logic; -- Reset the counter. (Active high.)
output: out std_logic -- Generates a logic high once the count has been reached.
);
end Counter;
architecture Behavioral of Counter is
signal count: unsigned(0 to 3);
begin
process(clk,reset)
begin
-- If reset goes high, reset the count.
if reset='1' then
count <= "0000"; -- Reset the counter.
output <= '0'; -- Set the output low.
elsif(clk'event and clk='1') then -- If not reset, and the rising edge of the input clock...
if enable='1' then -- If the counter is enabled...
if count=unsigned(value) then -- If the count reached the input value...
output <= '1'; -- Set the output high.
else
count <= count + 1; -- Increment the counter.
end if;
end if;
end if;
end process;
end Behavioral;