使用信号值的整数倍填充数组

时间:2013-10-25 11:52:13

标签: arrays loops vhdl

我有一个名为amux的数组,我想在数组中保存信号A的整数倍。下面的伪代码给出了一个想法:

amux(0) <= "00001101";
amux(1) <= amux(0);

....

amux(n) <= amux(n-1); 

我的完整代码如下:

-- n is 4 and m is 3, amux is an array, mzeros is 0's
regA: process(clk)
variable r : integer := 2**m;
begin
    if rising_edge(clk) then
        if ld_a = '1' then
            amux(0) <= std_logic_vector(to_unsigned((0),n*m+m));
            amux(1) <= mzeros & A;

            for i in 2 to r-1 loop 
              if (i mod 2) = 0 then
                   amux(i) <= amux(i/2)(n*m+m-2 downto 0) & '0';
                else
                  amux(i) <= std_logic_vector(unsigned(amux(i-1))+unsigned(amux(1)));
                end if;
            end loop;

        end if;
    end if;

结束流程regA;

我的当前实现输出所有“00000000”,除了amux(0)。我的方法有什么问题?

1 个答案:

答案 0 :(得分:0)

如果我们理解正确,问题是您在分配过程后不能立即在进程中使用信号值。分配的值仅在过程完成后可用。如果这是您打算做的,您可以使用变量来实现此目的。变量的值立即更新。

下面的代码示例应该接近您想要的内容:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity array_loader is
    generic (
        N: integer := 4;
        M: integer := 3;
        DATA_WIDTH: integer := N * M + M;
        ARRAY_DEPTH: integer := 2**M
    );
    port (
        clk: in std_logic;
        ld_a: in std_logic;
        A: in unsigned(DATA_WIDTH-1 downto 0)
    );
end;

architecture rtl of array_loader is
    type amux_type is array (0 to ARRAY_DEPTH-1) of unsigned(DATA_WIDTH-1 downto 0);
    signal amux: amux_type;

begin
    regA: process(clk)
        variable multiple: unsigned(DATA_WIDTH-1 downto 0);
    begin
        if rising_edge(clk) then
            if ld_a then
                multiple := to_unsigned(0, multiple);
                amux(0) <= multiple;

                for i in 1 to amux'high loop
                    multiple := multiple + A;
                    amux(i) <= multiple;
                end loop;
            end if;
        end if;
    end process;
end;

请注意,上述代码仅适用于VHDL-2008;在早期版本中,ld_a必须明确地与'1'进行比较,并且不可能使用通用常量NM来计算后续泛型的值