Question

这是刺激文件：

module final_stim;
reg [7:0] in,in_data;
reg clk,rst_n,rd,wr,rd_data,wr_data;
wire [7:0] out,out_wr;
wire[7:0]   d;
integer i;
reg kld,f;
reg [127:0]key;
wire [127:0] key_expand;
wire [7:0]out_data;
reg [7:0] k;
//wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [7:0] out_data1;

**//key_expand is da output which is giving 10 streams of size 128 bits.**
assign k1=key_expand[127:120];
assign k2=key_expand[119:112];
assign k3=key_expand[111:104];
assign k4=key_expand[103:96];
assign k5=key_expand[95:88];
assign k6=key_expand[87:80];
assign k7=key_expand[79:72];
assign k8=key_expand[71:64];
assign k9=key_expand[63:56];
assign k10=key_expand[55:48];
assign k11=key_expand[47:40];
assign k12=key_expand[39:32];
assign k13=key_expand[31:24];
assign k14=key_expand[23:16];
assign k15=key_expand[15:8];
assign k16=key_expand[7:0];

**// then the module of memory is instanciated.
//here k1 is sent as input.but i don know how to save the other values of k.
//i tried to use for loop but it dint help**
memory m1(clk,rst_n,rd, wr,k1,out_data1);
aes_sbox b(out,d);
initial 
begin
    clk=1'b1;
    rst_n=1'b0;
    #20
    rst_n = 1;
    wr_data=1'b1;
    in=8'hd4;

    #20
    in=8'h27;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h11;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'hae;
     rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'he0;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'hbf;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h98;
    rd_data=1'b0;
    wr_data=1'b1;

           #20
    in=8'hf1;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'hb8;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'hb4;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h5d;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'he5;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h1e;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h41;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h52;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    in=8'h30;
    rd_data=1'b0;
    wr_data=1'b1;

    #20
    wr_data=1'b0;

    #380
    rd_data=1'b1;

    #320
    rd_data = 1'b0;

    /////////////// 

    #10
    kld = 1'b1; 
    key=128'h 2b7e151628aed2a6abf7158809cf4f3c;

    #20 
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b0;

    #10
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    kld = 1'b0;
    key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
    wr = 1'b1;
    rd = 1'b1;

    #20
    wr = 1'b0;
    #20
    rd = 1'b1;
end

always
    #10 clk=~clk;
always@(posedge clk)
  begin
    #10000
    $stop;
  end

endmodule

我在clk的每个posedge有一个128位的比特流，即每个长度为128比特的总共10比特流。

我想将128位流分成8位，8位，并且必须将它们存储在宽度为8位的ram /内存中。

我是通过将8位，8位分配给大小为8位的线来实现的。这样就有16根电线。我正在使用双端口ram。当我在激励中调用内存模块时，我不知道如何输入，因为我有16条不同的电线，名为k1到k16。

//Key expansion module to generate 128 bit streams(key reffered to as stream)
//This code generates 10 keys of 128 bits each at each positive edge of clock
module key_expansion(kld,clk,key,key_expand);
input kld,clk;
input [127:0] key;
wire [31:0] w0,w1,w2,w3;
output [127:0] key_expand;
reg [31:0] w[3:0];

wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [31:0] c0,c1,c2,c3;
wire    [31:0]  tmp_w;
wire    [31:0]  subword;
wire    [31:0]  rcon;
assign w0 = w[0];
assign w1 = w[1];
assign w2 = w[2];
assign w3 = w[3];
always @(posedge clk)   w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk)   w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk)   w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk)   w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0(    .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1(    .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2(    .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3(    .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0(    .clk(clk), .kld(kld), .out_rcon(rcon));
assign key_expand={w0,w1,w2,w3};
endmodule
//stimulus for key generation
module stim_key_exp;
reg kld ,clk;
reg [127:0]key;
wire [127:0] key_expand;
key_expansion x(kld,clk,key,key_expand);
initial 
begin
    clk=1'b1;
    kld = 1'b1;
    #20 
    kld=1'b0;
    key=128'h 2b28ab097eaef7cf15d2154f16a6883c;
end  
always 
#5 clk=~clk;
always@(posedge clk)
  begin
    $monitor($time," key_expand=%h\n",key_expand); 
    #110
    $stop;
  end
endmodule

我想将长度为128位的每个密钥分成8位块并存储它们。

要考虑的一件事是在时钟的每个上升沿生成新密钥。

在生成下一个密钥之前存储一个密钥需要什么。

Answer 1

您需要一个不同的存储器模块或一个总线多路复用器（移位寄存器），它可以将128个流序列化为16倍更高时钟的8位流。

从简单和实用的角度来看，我的建议是使用不同的内存块。实际上，128位寄存器似乎就足够了。请注意，您的测试仅使用一个密钥，因此无论如何都不会检查内存的功能。

在尝试修复任何内容之前，确实要清理代码。 ouut真的是一个很好的变量名吗？

如何在verilog中存储ram中的数据

1 个答案: