Question

我正在使用xilinx编写一个骰子或掷骰子游戏，用于spartan-6 nexys 3板。

我收到这些错误，说'if'或'begin'附近的语法错误。我知道我有正确的库，我相信我没有任何愚蠢的语法错误（尽管人们绝对不能确定这一点）。

我希望有经验的VHDL作曲家可以指出我在哪里出错了。提前谢谢！

        library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.numeric_bit.ALL;

    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    use IEEE.NUMERIC_STD.ALL;

    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    library UNISIM;
    use UNISIM.VComponents.all;

    entity DiceGame is
         Port ( Rb : in  STD_LOGIC;
                  Reset : in  STD_LOGIC;
                  CLK : in  STD_LOGIC;
                  Sum : in  integer range 2 to 12;
                  Roll : out  STD_LOGIC;
                  Win : out  STD_LOGIC;
                  Lose : out  STD_LOGIC);
    end DiceGame;

    architecture DiceBehave of DiceGame is
    signal State: integer range 0 to 5;
    signal Nextstate: integer range 0 to 5;
    signal Point: integer range 2 to 12;
    signal Sp: STD_LOGIC;

    begin
        proces(Rb, Reset, Sum, State)
        begin
            Sp <= '0'; Roll<='0'; Win <='0'; Lose<='0';

            case State is

                when 0 => 
                    if Rb='1' then Nextstate <= 1; 
                    end if;

                when 1 =>
                    if Rb='1' then Roll='1';
                    elsif Sum=7 or sum=11 then Nextstate <= 2;
                    else if Sum=2 or Sum=3 or Sum=12 then Nextstate <= 3;
                    else Sp='1'; Nextstate <= 4;
                    end if;

                when 2 =>
                    win <='1';
                    if Reset='1' then Nextstate <= 0;
                    end if;

                when 3 =>
                    Lose <= '1';
                    if Reset='1' then Nextstate <=0;
                    end if;

                when 4 =>
                    if Rb='1' then Nextstate <= 5;
                    --else NextState <=4;
                    end if;

                when 5 =>
                    if Rb='1' then Roll='1';
                    elsif Sum = Point then Nextstate <=2;
                    elsif Sum= 7 then Nextstate <=3;
                    else Nextstate <=4;
                    end if;

            end case;

        end process;

        Process(CLK)
        begin

            if CLK'event and CLK='1' then State<=Nextstate;
                if Sp='1'then Point<= Sum;
                end if;
            end if;

        end process;

    end DiceBehave;

以下是我的错误：

ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 51: Syntax error near "begin".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 54: Syntax error near "case".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 58: Syntax error near "if".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 63: Syntax error near "else".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 64: Syntax error near "else".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 65: Syntax error near "if".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 69: Syntax error near "if".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 70: Syntax error near "if".  
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital   
WARNING:HDLCompiler:1369 - "\\cdc-data\susers\lreves\Advanced Digital   Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 91: Possible infinite loop; process does not have a wait statement  
ERROR:HDLCompiler:854 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 43: Unit <dicebehave> ignored due to previous errors.  
VHDL file \\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd ignored due to errors  
-->   

Total memory usage is 221592 kilobytes  

Number of errors   :   15 (   0 filtered)  
Number of warnings :    1 (   0 filtered)  
Number of infos    :    0 (   0 filtered)  


Process "Synthesize - XST" failed

Answer 1

第50行第51行拼写错误process（第54,58行将崩溃下一个错误）

第63行Roll='1'应为Roll <= '1'（将崩溃错误第64,65行）。

第69行：else Sp ='1'; Nextstate <= 4;应为else Sp <= '1'; Nextstate <= 4;

第68行:(未列为错误）else if应为elsif

第88行:(未列为错误）then Roll = '1';应为then Roll <= '1';

然后分析和阐述（我们没有声称它是正确的，重新格式化缩进和空白的冲动几乎是压倒性的。）

（这些告诉我们你应该使用一致的缩进和空格来突出这些）。

另请注意，必要的唯一使用条款是

use IEEE.STD_LOGIC_1164.ALL;

其余的使用条款是噪音。

（这里希望依靠我的手指和脚趾从错误信息和VHDL样本不匹配中得到原始行号。）

Xilinx语法错误：HDLCompiler：806

1 个答案: