Question

我是Verilog和FPGA的新手。所以，如果我犯了任何错误，请保持温和。

我试图在Verilog上制作一个I2C协议，然后我输入了这个人输入的内容（video on YouTube that explains how to make a I2C BUS protocol）

module step1(
input wire clk,
input wire reset,
output reg i2c_sda,
output reg i2c_scl
);

//goal is to write to device addres 0x50, 0xaa

localparam STATE_IDLE = 0;
localparam STATE_START = 1;
localparam STATE_ADDR = 2;
localparam STATE_RW = 3;
localparam STATE_WACK = 4;
localparam STATE_DATA = 5;
localparam STATE_STOP = 6;
localparam STATE_WACK2 = 7;
reg [7:0] state;
reg [6:0] addr;
reg [7:0] data; 
reg [7:0] count;

always @(posedge clk) begin
    if (reset == 1) begin
        state <= 0;
        i2c_sda <= 1;
        i2c_scl <= 1;
        addr <= 7'h50;
        count <= 8'd0;
        data <= 8'haa;
    end
    else begin
        case(state)

            STATE_IDLE: begin //idle
                i2c_sda <= 1;
                state <= STATE_START;
            end // end state idle

            STATE_START: begin //start  
                i2c_sda <= 1;
                state <= STATE_ADDR;
                count <= 6;
            end // end of state start

            STATE_ADDR: begin // fisrt addres bit or the most significant adress bit
                i2c_sda <= addr[count];
                if (count == 0) state <= STATE_RW;
                else count <= count - 1;
            end // end of state ADDR

            STATE_RW: begin // Read or Write opperation
                i2c_sda <= 1;
                state <= STATE_WACK;
            end // end state RW

            STATE_WACK: begin
                state <= STATE_DATA;
                count <= 7;
            end // end of state WACK

            STATE_DATA: begin
                i2c_sda <= data[count];
                if (count == 0) state <= STATE_WACK2;
                else count <= count-1;
            end // end of state DATA

            STATE_WACK2: begin
                state <= STATE_STOP;
            end // end state WACK2

            STATE_STOP: begin
                i2c_sda <= 1;
                state <= STATE_IDLE;
            end // end of state STOP

        end// end of case
    end // end of the else
  end // end of if
endmodule

但是，当我尝试编译时弹出以下错误。我真的不明白为什么，因为一切都是正确的（至少对我而言）：

ERROR:HDLCompiler:806 - "/home/yunta23/Documentos/Digital1/VideosYou/primero/step1/step1.v" Line 97: Syntax error near "end".

关于这个错误的任何解释都会帮助我进入决赛！非常感谢你们。

Answer 1

case语句需要endcase关键字，而不是end关键字。变化：

    end// end of case

为：

    endcase

错误：HDLCompiler：806 ...“end”附近的语法错误

1 个答案: