我正在尝试合成并实施与参考设计附加信息相关联的参考设计。以下文件的部分：
http://www.xilinx.com/support/documentation/application_notes/xapp879.pdf
在尝试合成参考设计（没有任何修改）时，我收到以下错误消息，其中V10连接到＆＃39; CLKIN＆＃39;从UCF文件中的参考设计输入top.v文件。 （UCF文件仅声明将LVCMOS33用于CLKIN并将其绑定到V10。）
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <CLK> is placed at site <V10>. The corresponding BUFG component
<t0/BUFG_IN> is placed at site <BUFGMUX_X3Y7>. There is only a select set of
IOBs that can use the fast path to the Clocker buffer, and they are not being
used. You may want to analyze why this problem exists and correct it. If this
sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
我正在使用Project Navigator 14.7（使用Verilog编码），我的目标是存在于PCB板上的Spartan-6 FPGA，其参考手册在此处：http://numato.com/productdoc/saturn/SaturnSpartan6ModuleV1.pdf
我认为top.v文件中的PLL或某些BUFG / IBUFG实例需要手动重定位到UCF文件中的其他站点，但到目前为止，我所尝试过的任何内容都没有。在我的PCB上，V10连接到100 MHz振荡器。请注意，我不能将另一个时钟信号路由到FPGA板，除非我使用其中一个通用I / O端口，我相信它具有低驱动强度。
非常感谢任何帮助！