我有一个项目,我正在走过BRAM。我在其中一个增加地址的部分有一个问题。我复制了我在下面的状态机中使用的逻辑。请在这里指出我的错误,我的增量是不稳定的,并没有按预期发生。
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity test is
port (clk : in std_logic;
count : out std_logic_vector(9 downto 0);
reset : in std_logic);
end test;
architecture Behavioral of test is
signal c : std_logic_vector(9 downto 0) := (others => '0');
type state_type is (state1, state2, state3, state4);
signal gcd_cs, gcd_ns : state_type;
begin
count <= c;
process(clk, reset, c)
begin
if(clk'event and clk = '1') then
if(reset = '1')then
gcd_cs <= state1;
else
gcd_cs <= gcd_ns;
end if;
end if;
case gcd_cs is
when state1 =>
if(reset = '0') then
gcd_cs <= state2;
else
gcd_cs <= state1;
end if;
when state2 =>
if(c > "0000001111") then
gcd_cs <= state4;
else
gcd_cs <= state3;
end if;
when state3 =>
c <= c+'1';
gcd_ns <= state2;
when state4 =>
gcd_ns <= state4;
end case;
end process;
end Behavioral;
答案 0 :(得分:0)
你在这里遇到了很多问题。
IF clk'event
之外)注意有关锁存器,灵敏度列表等的编译器警告
将下一状态计算更改为并发逻辑。该过程应该只更新作为寄存器的信号(基本上是D触发器)。
这样的事情:
PROCESS (clk,reset)
BEGIN
IF reset = '1' THEN
gcd_cs <= state1; -- for asynchronous reset
c <= (OTHERS => '0');
ELSIF RISING_EDGE(clk) THEN
IF reset = '1' THEN
gcd_cs <= state1; -- for synchronous reset
c <= (OTHERS => '0');
ELSE
IF gcd_cs = state3 THEN
c <= c + 1;
END IF;
gcd_cs <= gcd_ns;
END IF;
END IF;
END PROCESS;
gcd_ns <= state2 WHEN gcd_cs = state1 ELSE
state4 WHEN gcd_cs = state2 AND c > "0000001111" ELSE
state3 WHEN gcd_cs = state2 AND NOT (c > "0000001111") ELSE
state2 WHEN gcd_cs = state3 ELSE
state4 WHEN gcd_cs = state4;
只选择两种重置行为中的一种。