Question

/*
S0= highway GREEN county RED
S1= Highway YELLOW County RED
S2= highway RED County RED
S3= highway RED County GREEN
s4= Highway RED County YELLOW
*/

/*
X checks the movement on County Road
  =1 means CARS ARE THERE
  =0 means CARS ARE NOT THERE
*/

module sig_ctrl(
  hwy,
  county,
  x,
  clock,
  clear);

  output [1:0] hwy,county;
  reg    [1:0] hwy,county;
  reg    [2:0] pre_state,  next_state;

  reg i = 0;
  input x, clock, clear;

  parameter RED    = 2'b00,
            YELLOW = 2'b01,
            GREEN  = 2'b10;

  parameter s0 = 3'b000,
            s1 = 3'b001,
            s2 = 3'b010,
            s3 = 3'b011,
            s4 = 3'b100,
            s5 = 3'b101;

  always @(posedge clock) begin
    if (clear)
      pre_state <= s0;
    else
      pre_state <= next_state;
  end

  always @(pre_state or x) begin
    case(pre_state)
      s0 : begin
        if (x) 
          next_state = s1;
        else
          next_state = s0;
      end

      s1: @(posedge clock) begin
        begin
          while (i<=3)
            i=i+1;
        end
        begin
          next_state = s2;
        end
      end

      s2: @(posedge clock) begin
        next_state = s3;
      end

      s3: begin
        if(x)
          next_state = s3;
        else
          next_state = s4;
      end
      s4: @(posedge clock) begin
        while (i<=3)
          i=i+1;
        next_state = s0;
      end

      default : next_state = s0;
    endcase
  end

  always @(pre_state) begin
   case(pre_state)
    default :begin hwy = GREEN;county = RED;end
    s0 : ;
    s1 : hwy = YELLOW;
    s2 : hwy = RED;
    s3 : begin
      hwy    = RED;
      county = GREEN;
    end
    s4 : begin
      hwy    = RED;
      county = YELLOW;
    end
  endcase
end
endmodule

这是交通灯模拟的verilog代码.... 在编译这个代码时..我在第45行（其中＆＃39;总是@（pre_state或x）＆＃39;被写入）得到一个错误作为合成限制。请帮我删除它。

谢谢

Answer 1

always块的正文中不允许使用时间阻止语句。 @(posedge clock)中的always @(pre_state or x)是非法的。如果您想在更改状态之前再等一个时钟周期，那么我建议您添加一个计数器。

while - 循环也不可合成。循环只能在循环计数恒定时合成，ex for (i=0;i<3;i=i+1) begin /* nothing that assigns i */ end。很明显，你从未模拟过你的代码，因为i是一个位，总是小于3并且是一个无限循环。即使i具有适当的范围，它也不会在代码中执行任何操作。

其他问题/建议：

hwy和county将合成复杂的锁存逻辑。将其always @(pre_state)更改为always @(posedge clock)并将阻止（=）的分配更改为非阻止（<=）
将always @(pre_state or x)更改为always @*或always @(*)。您目前使用的是IEEE1364-1995语法。这是合法的，但如果不维护敏感度列表，则存在创建复杂锁存逻辑的风险。 @*和@(*)是同义词。它们被添加到IEEE1364-2001中，用于自动灵敏度列表。

input和output s。我建议使用IEEE1364-2001的ANSI样式作为替代方案。键入较少，特别是当有很长的端口列表时：

module sig_ctrl(
    output reg [1:0] hwy,county,
    input x,clock,clear ); /* This is IEEE1364-2001's ANSI style */

  reg [2:0]pre_state,next_state;
  integer i = 0;
/...

合成限制......这是什么..？

1 个答案: