基本上,这个Synplify输出意味着什么:
@N: MT206 |Auto Constrain mode is enabled
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.zf is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.cf is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.pc[7:0] is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.intra[1:0] is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.tv[15:0] is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.port[3:0] is being ignored.
@W: FX1039 :"c:\sftp_root\x002\tinyproc.v":61:3:61:8|User-specified initial value defined for instance tp.instr[15:0] is being ignored.
FPGA上没有可指定初始寄存器状态吗?我的目标是iCE40系列(特别是iCE40HX1K - “冰棍”平台)。
答案 0 :(得分:0)
此警告必须表示目标FPGA不支持寄存器的初始值。如果您有如下声明,Synplify将忽略初始值。
reg zf = 1'b0;
合成将按照声明如下进行。
reg zf;
您可以做的是通过复位信号初始化寄存器。如果您已经这样做,则可以忽略警告。不过,我会删除初始值,以避免模拟和合成之间任何潜在的不匹配。