LIFO内存vhdl代码了解

时间:2014-05-31 17:45:24

标签: vhdl lifo

我有一个生命记忆的代码我不明白为什么在27行(if(last = n-2)然后full< ='1';结束if;) last 表示它不等于n-1。 如果有人能向我解释,我真的很感激。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lifo is
  generic(n : natural := 4);
  port(Din         : in  std_logic_vector(3 downto 0);
       Dout        : out std_logic_vector(3 downto 0);
       wr          : in  std_logic;
       rd          : in  std_logic;
       empty, full : out std_logic;
       clk         : in  std_logic);
end entity lifo;

architecture arh of lifo is
  type memorie is array(0 to n-1) of std_logic_vector(3 downto 0);
  signal mem  : memorie := (others => (others => '0'));
  signal last : integer range -1 to n-1;
begin
  process(clk)
  begin
    if (rising_edge(clk)) and (wr = '1') then
      if (last = n-1) then null;
      else
        if(last = n-2) then full <= '1'; end if;
        if(last = -1) then empty <= '0'; end if;
        mem(last + 1)            <= Din;
        last                     <= last + 1;
      end if;
    elsif (rising_edge(clk)) and (rd = '1') then
      if(last = -1) then null;
      else
        Dout                     <= mem(last);
        last                     <= last - 1; full <= '0';
        if(last = -1) then empty <= '1'; end if;
      end if;
    end if;
  end process;
end architecture arh;

1 个答案:

答案 0 :(得分:1)

last位于range -1 to n-1,当last为n-1时,则表示完整LIFO,full必须为高('1'

接受写入后,lastlast <= last + 1加1。clk。在同一上升的full边缘,确定last是否应该变高,如果此写入将使LIFO满,则是这种情况。写入之后,last = n-2的值为last + 1(接受写入时为+1),如果等于n-1(n-1表示已满),则LIFO为满。因此,写入后的完整条件是最后+ 1 = n-1,然后写为rising_edge(clk)

此外,如果代码不能立即起作用,可以通过多种方式改进代码,例如:单null,添加重置,通过否定条件跳过if语句,在同一周期中添加写和读操作的处理,删除死代码(最终{{1}})。