Question

--
-- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1
--
-- Created:
--          by - 294162.UNKNOWN (VD1210)
--          at - 14:19:36 10-04-2015
--
-- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY WORK;
USE WORK.CALC_PKG.ALL;
LIBRARY di_lib;
USE di_lib.calc_pkg.all;
USE ieee.NUMERIC_STD.all;

ENTITY ShiftRegister1 IS
   PORT( 
      d_out       : OUT    Std_Logic_Vector (7 DOWNTO 0);
      multiplexer : IN     Std_Logic_Vector (7 DOWNTO 0);
      carry       : IN     std_logic;
      load_out    : IN     std_logic;
      f_code      : IN     std_logic_vector (2 DOWNTO 0);
      out_loaded  : OUT    std_logic
   );

-- Declarations

END ShiftRegister1 ;

--
ARCHITECTURE ShiftRegister1 OF ShiftRegister1 IS
BEGIN

  ShiftRegister1 : process

  variable remember, multiplexer_var       : std_logic_vector(7 DOWNTO 0);
  variable state          : std_logic_vector(2 DOWNTO 0);
  variable counter        : integer := 0; 
        begin

          state := f_code;

        case state is

        when "000" => 
            d_out <= multiplexer;

        when "001" =>
            d_out <= multiplexer;

        when "010" =>
                multiplexer_var := multiplexer;
            if load_out = '1' then 
              if carry = '1' then
                --shifting is done without function SRL
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '1';
                d_out <= remember;
                out_loaded <= '1';

              elsif  carry = '0' then
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '0';
                d_out <= remember;
                out_loaded <= '1';
              end if;
            end if;

        when "011" =>
            if load_out = '1' then
              d_out <= multiplexer;
              out_loaded <= '1';
            end if;

        when others => null;

        end case;
   end process;

END ARCHITECTURE ShiftRegister1;

- 错误提供 -

- 编译shiftregister1的架构shiftregister1   **警告：[2]＆lt; ...＆gt; vhd（109）:( vcom-1090）可能的无限循环：进程不包含WAIT语句。
  警告：无法创建未映射的图书馆工作

问题：可能在这段代码中可能出现无限循环？

Answer 1

在VHDL中，进程的执行时间是瞬时的。此外，一旦完成一个过程就会重新执行。因此，您的过程形成了一个无限循环。

要解决此问题，是添加wait语句还是使用敏感列表。具有灵敏度列表的过程仅在其中一个灵敏度列表信号发生变化时执行。类似的东西：

process(load_out, carry, multiplexer, f_code)

您必须确保在灵敏度列表中添加该过程使用的所有信号，否则您将得到模拟不匹配，因为合成会忽略灵敏度列表。

vhdl代码理解，如果有关于可能的无限循环的modelsim错误

1 个答案: