VHDL无限循环

时间:2013-03-30 16:16:22

标签: vhdl modelsim

我正在编写一小段代码,一次采用32位输入并输出2位。基于模拟尝试,我相信我在while循环中遇到了无限循环问题。与我看过的其他循环示例相比,一切看起来都合适。我有什么可能做错的任何线索?

library ieee;
use ieee.std_logic_1164.all;

entity regA is 
port(mpcnd: in std_logic_vector(31 downto 0);
      clk: in std_logic;
      twobits: out std_logic_vector(1 downto 0));
end regA;

architecture behavior of regA is 
begin
process
variable count: integer;
begin
count := 0;
while (count < 32) loop
    if rising_edge(clk) then
    twobits(0) <= mpcnd(count);
    twobits(1) <= mpcnd(count+1);
    count := count + 2;
    end if;
end loop;
end process;
end behavior;

1 个答案:

答案 0 :(得分:1)

对于进程,您需要敏感列表或等待语句。您的流程的(不可合成但可模拟的)版本可能如下所示:

process
    variable count: integer;
begin
    count := 0;
    while (count < 32) loop
    wait until rising_edge(clk);-- if rising_edge(clk) then
    twobits(0) <= mpcnd(count);
    twobits(1) <= mpcnd(count+1);
    count := count + 2;
--end if;
end loop;
end process;