Question

我想使用STD_LOGIC_VECTOR输入，它应转换为Unsigned作为Case语句中的选择器，如下所示：

`  port ( clk_24 : in std_logic;
         frequency : in STD_LOGIC_VECTOR(2 downto 0);
         led : out std_logic);
case unsigned(frequency) is
  when to_unsigned(1, 3) => counterlimit <= to_unsigned(48000000, 32);
  when to_unsigned(2, 3) => counterlimit <= to_unsigned(24000000, 32);
  when to_unsigned(3, 3) => counterlimit <= to_unsigned(12000000, 32);
  when to_unsigned(4, 3) => counterlimit <= to_unsigned(6000000, 32);
  when to_unsigned(5, 3) => counterlimit <= to_unsigned(3000000, 32);
  when to_unsigned(6, 3) => counterlimit <= to_unsigned(1500000, 32);
  when to_unsigned(7, 3) => counterlimit <= to_unsigned(750000, 32);            
end case;

` 但是我得到了错误：

第48行。选择器（UNSIGNED类型的类型转换）是一个不受约束的数组。

有人知道，问题可能是什么？

Answer 1

除了fru1bat的建议之外，您还需要一个涵盖0和8到整数＆MAX;或中间变量的其他选项，其中包含范围约束的选项0：

其他选择0到整数＆＃39; MAX：

UNLABELED:
    process(frequency)
    begin
        case to_integer(unsigned(frequency)) is
            when 1 => counterlimit <= to_unsigned(48000000, 32);
            when 2 => counterlimit <= to_unsigned(24000000, 32);
            when 3 => counterlimit <= to_unsigned(12000000, 32);
            when 4 => counterlimit <= to_unsigned(6000000, 32);
            when 5 => counterlimit <= to_unsigned(3000000, 32);
            when 6 => counterlimit <= to_unsigned(1500000, 32);
            when 7 => counterlimit <= to_unsigned(750000, 32);
         -- when 0 to integer'MAX;
            when others => counterlimit <= to_unsigned(96000000, 32);
        end case;
    end process;

范围约束变量：

UNLABELED:
    process(frequency)
    variable freq:      integer range 0 to 7;
    begin
        freq := to_integer(unsigned(frequency));
        case freq is
            when 0 => counterlimit <= to_unsigned(96000000, 32);
            when 1 => counterlimit <= to_unsigned(48000000, 32);
            when 2 => counterlimit <= to_unsigned(24000000, 32);
            when 3 => counterlimit <= to_unsigned(12000000, 32);
            when 4 => counterlimit <= to_unsigned(6000000, 32);
            when 5 => counterlimit <= to_unsigned(3000000, 32);
            when 6 => counterlimit <= to_unsigned(1500000, 32);
            when 7 => counterlimit <= to_unsigned(750000, 32);
        end case;
    end process;

0和8到整数＆＃39; MAX情况的原因是在to_integer转换后继续自然＆＃39;范围时评估的匿名自然，而freq在其声明中被约束。

Answer 2

不确定为什么它认为它是一个无约束的数组，但你可以（应该？）执行以下操作：

case to_integer(unsigned(frequency)) is
  when 1 =>
    ...

易于阅读，应该编译得很好。

VHDL：使用未签名的案例选择器

2 个答案: