单位无符号信号

时间:2018-03-14 16:13:57

标签: vhdl

看到以下示例代码:

architecture arch of disp_mux is
  constant N:integer :=18;
  signal q_reg, q_next: unsigned(N-1 downto 0);
  signal sel: std_logic_vector(1 downto 0);
begin
  process(clk, reset)
  begin
    if reset='1' then
      q_reg <= (others=>'0');
    elsif (clk'event and clk='1') then
      q_reg <= q_next;
    end if;
  end process;
  q_next <= q_reg + 1;
  sel <= std_logic_vector(q_reg(N-1 downto N-2));
  process(sel, ...)
  begin
    case sel is...
    end case;
  end process;
end arch;

如果您从未将1写入resetq_reg的价值是多少?如果q_next <= q_reg + 1;q_reg UUUUUUUUUUUUUUUUUUa.nav-toggle会发生什么,这是我怀疑的。

1 个答案:

答案 0 :(得分:1)

如果您从未向reset写1,则q_reg"UUUUUUUUUUUUUUUUUU",执行q_next <= q_reg + 1q_next成为"XXXXXXXXXXXXXXXXXX"