如果输入有签名或未签名,加法器是否关心?

时间:2016-09-21 16:38:05

标签: vhdl

我本来应该设计一个3位2的补码加法器,到目前为止,我已经混合了匹配的正负输入,似乎得到了正确的输出。普通加法器和2补码加法器之间有什么区别吗?

首先,我设计了3位加法器(门级),我已经为最终执行添加了门,所以请忽略它。想象一下:

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这是我的代码(我知道我可以更好地命名我的信号)。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

    entity B_addr is port(
    A2,A1,A0,B2,B1,B0 : in std_logic;
    Cout,Sum2,Sum1,Sum0 : out std_logic
    );
end B_addr;

architecture B_addr_arch of B_addr is

signal net0, net1, net2, net3, net4, net5, net6, net7, net8, net9, net10, net11 : std_logic;

begin
    net0 <= A0 xor B0;
    net1 <= '0';
    net2 <= net0 and net1;
    net3 <= A0 and B0;
    net4 <= net2 or net3;
    net5 <= A1 xor B1;
    net6 <= net5 and net4;
    net7 <= A1 and B1;
    net8 <= net6 or net7;
    net9 <= A2 xor B2;
    net10 <= net9 and net8;
    net11 <= A2 and B2;
    Sum0 <= net0 xor net1;
    Sum1 <= net5 xor net4;
    Sum2 <= net9 xor net8;
    Cout <= net10 or net11;

end B_addr_arch;

我认为我想回答的主要问题是,这是否足以补充2?

0 个答案:

没有答案