Question

此代码选择LED或7段显示，以显示我通过开关输入的8位数据。我通过按钮选择LED或7段。当我尝试在我的nexys2板上运行它时，led部件工作正常但是当我按下按钮时，所选的7段发光并且也随着LED发光改变其值。此外，只有当我再次按下按钮时，7段才会改变它的值。我是一个新手，我认为我在制作一个好的逻辑或问题是什么？任何帮助将不胜感激！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity selector is 
Port ( clk: in STD_LOGIC;
sel : in  STD_LOGIC;
comb : in STD_LOGIC_VECTOR (7 downto 0);
segment : out  STD_LOGIC_VECTOR (3 downto 0);
number : out  STD_LOGIC_VECTOR (6 downto 0);
led: out STD_LOGIC_VECTOR (7 downto 0));
end selector;

architecture Behavioral of selector is

begin
process (clk, comb, sel) begin
    if (clk'event and clk = '1') then
        if sel = '1' then
            segment <= "1110";
                case (comb) is 
            when "00000000" => number <= "0000001"; --0
            when "00000001" => number <= "1001111"; --1
            when "00000010" => number <= "0010010"; --2
            when "00000011" => number <= "0000110"; --3
            when "00000100" => number <= "1001100"; --4
            when "00000101" => number <= "0100100"; --5
            when "00000110" => number <= "0100000"; --6
            when "00000111" => number <= "0001111"; --7
            when "00001000" => number <= "0000000"; --8
            when "00001001" => number <= "0000100"; --9
            when others => number <= "1111111"; -- off
        end case;
    elsif sel = '0' then 
                case (comb) is 
            when "00000000" => led <= "00000000"; --0
            when "00000001" => led <= "00000001"; --1
            when "00000010" => led <= "00000011"; --2
            when "00000011" => led <= "00000111"; --3
            when "00000100" => led <= "00001111"; --4
            when "00000101" => led <= "00011111"; --5
            when "00000110" => led <= "00111111"; --6
            when "00000111" => led <= "01111111"; --7
            when "00001000" => led <= "11111111"; --8
            when others => led <= "00000000"; -- off
                end case;
    end if;
end if;
end process;

end Behavioral;

Answer 1

您没有更改未选择的输出值，因此它将保持最后分配的状态。

此外，您的代码只会对时钟的上升沿产生影响，因此灵敏度列表可以减少到(clk)（此时隐含clk'event）。

VHDL代码在Nexys2上无法正常运行

1 个答案: