Question

我的实验室合作伙伴和我无法弄清楚为什么我们在此组件的波形模拟中没有获得任何输出。我们自己模拟了组件并获得了预期的行为，但是嵌套在实体内部，输出信号没有被初始化，只有未初始化的＆＃39; X＆＃39;响应。

这是顶级实体中的组件声明：

 99     component CH is
100     Port (  clk                 : in std_logic;
101                 X                   : in std_logic_vector(31 downto 0);
102                 Y                   : in std_logic_vector(31 downto 0);
103                 Z                   : in std_logic_vector(31 downto 0);    
104                 CH_OUT          : out std_logic_vector(31 downto 0)
105             );
106     end component;

这是我们用来分配输入/输出的过程：

289     round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig, T1_sig)
290     begin
291             CH_X_in <= e_sig;
292             CH_Y_in <= f_sig;
293             CH_Z_in <= g_sig;
294             T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
295     end process;

这是CH组件的代码

  1 library IEEE;
  2 use IEEE.STD_LOGIC_1164.ALL;
  3 use IEEE.STD_LOGIC_ARITH.ALL;
  4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5     
  6 -- CH is defined as (X AND Y) XOR (X' AND Z)
  7 -- Verified working
  8 
  9 entity CH is
 10     Port (  clk                 : in std_logic;
 11                 X                   : in std_logic_vector(31 downto 0);
 12                 Y                   : in std_logic_vector(31 downto 0);
 13                 Z                   : in std_logic_vector(31 downto 0);
 14                 CH_OUT          : out std_logic_vector(31 downto 0)
 15             );
 16 end CH;
 17 
 18 architecture Behavioral of CH is
 19 
 20 begin
 21 
 22     Compute : process (clk, X, Y, Z)
 23     begin
 24 
 25         CH_OUT <= (X and Y) xor ((not X) and Z);
 26 
 27     end process;
 28 
 29 end Behavioral;

这些问题类似，但未在本文中解决此问题，因为 -

VHDL component and outputs based on generic - 不涉及流程

Simple VHDL Problem with synchronous/asynchronous logic - 不涉及从系统分配给组件的组件和信号

Why doesn't my code produce output? - 我想我们的代码有正确的敏感度列表

Answer 1

您应该查看工具的输出以获取警告。听起来你有一个未绑定的组件CH。

使用：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--  3 use IEEE.STD_LOGIC_ARITH.ALL;
--  4 use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- CH is defined as (X AND Y) XOR (X' AND Z)
-- Verified working

entity CH is
    Port (  clk                 : in std_logic;
                 X                   : in std_logic_vector(31 downto 0);
                 Y                   : in std_logic_vector(31 downto 0);
                 Z                   : in std_logic_vector(31 downto 0);
                 CH_OUT          : out std_logic_vector(31 downto 0)
             );
end CH;

 architecture Behavioral of CH is

begin

Compute : process (clk, X, Y, Z)
    begin

        CH_OUT <= (X and Y) xor ((not X) and Z);

    end process;

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ch_comp is
end entity;

architecture foo of ch_comp is

    component CH is
        Port (  clk                 : in std_logic;
                    X                   : in std_logic_vector(31 downto 0);
                    Y                   : in std_logic_vector(31 downto 0);
                    Z                   : in std_logic_vector(31 downto 0);    
                    CH_OUT          : out std_logic_vector(31 downto 0)
        );
    end component;

    signal CH_X_in:     std_logic_vector(31 downto 0);
    signal CH_Y_in:     std_logic_vector(31 downto 0);
    signal CH_Z_in:     std_logic_vector(31 downto 0);
    signal CH_OUT_sig:  std_logic_vector(31 downto 0);

    signal e_sig:       std_logic_vector(31 downto 0) := X"feedface";
    signal f_sig:       std_logic_vector(31 downto 0) := X"deadbeef";
    signal g_sig:       std_logic_vector(31 downto 0) := X"ffffffff";
    signal T1_sig:      std_logic_vector(31 downto 0);
    signal clk:         std_logic := '0';
begin

round_compute2 : process (clk, CH_OUT_sig, e_sig, f_sig, g_sig) --, T1_sig)
     begin
             CH_X_in <= e_sig;
             CH_Y_in <= f_sig;
             CH_Z_in <= g_sig;
             T1_sig <= std_logic_vector(unsigned(CH_OUT_sig));
     end process;

UUT:
    CH
        port map (
            clk => clk,
            X => CH_X_in,
            Y => CH_Y_in,
            Z => CH_Z_in,
            CH_OUT => CH_OUT_sig
        );
TEST:
    process
    begin
        wait for 10 ns;
        e_sig <= X"deadface";
        f_sig <= X"facebeef";
        g_sig <= X"EEEEFFFF";
        wait for 10 ns;
        wait;

    end process;

end architecture;

我得到了：

CH simulation

也就是说，它似乎不会仅在CH_out_sig或T1_sig上展示未初始化的＆＃39;

看起来你还没有透露足够的或你的VHDL设计描述或足够的工具构建和模拟过程，以便第三方看到你出错的地方。

VHDL - 三层过程但模拟中没有来自逻辑单元的输出

1 个答案: