Question

这是我的代码：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY AND_Bank_Test IS
END AND_Bank_Test;

ARCHITECTURE behavior OF AND_Bank_Test IS 

 -- Component Declaration for the Unit Under Test (UUT)

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(7 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(7 downto 0)
    );
END COMPONENT;


   --Inputs

signal Input : std_logic_vector(7 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(7 downto 0);

-- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 


BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

   -- Stimulus process

   stim_proc: process
    begin       
-- hold reset state for 100 ns.

    wait for 100 ns;    

    Input <= "00000001" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "00111011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "01110111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110000" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "11110011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "01110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "11111111" ; AND_Bit <= 1; 
    wait for 100 ns;    
wait;
end process;

END;

这是我得到的错误：

Type std_logic does not match with the integer literal (this refers to Input <= "00000001" ; AND_Bit <= 0; )

我用这个替换了我的代码：

ENTITY AND_Bank_Test是 END AND_Bank_Test;

AND_Bank_Test的架构行为是

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(15 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(15 downto 0)
    );

END COMPONENT;

- 输入

signal Input : std_logic_vector(15 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(15 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

- 刺激过程

stim_proc：进程开始
- 保持复位状态100 ns。

    wait for 100 ns;    

    Input <= "0000000000000001" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000000111011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000001110111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110000" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000011110011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000001110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000011111111" ; AND_Bit <= '1'; 
    wait for 100 ns;

等待; 结束过程;

END;

这是运行AND银行测试的正确方法吗？为什么不能只用8位运行它？

Answer 1

您需要使用单引号，例如：

Input <= "00000001" ; AND_Bit <= '0';

如果您没有使用单引号，则假定您要为AND_Bit分配一个整数值，这就是为什么它会给您一个错误。

Answer 2

关于您的错误，AND_Bit是std_logic。您必须在测试平台而不是AND_BIT <= '0';中编写AND_BIT <= 0;这就是为什么模拟器将0视为整数而不是一点。对于注释中的第二个错误，您更改了IN and OUT的大小，即16位，但在测试平台中，您将8位作为输入。所以相应地改变大小。

无法运行和银行测试平台？

2 个答案: