Question

我目前正在开展一个项目，我必须采用Fibonacci算法高级描述（C）并将其转换为用VHDL编写的RTL模块。为此，需要在可合成的VHDL代码中转换这种高级描述，即，必须以IC原型中广为人知的方法编写用于数据路径和有限状态机（FSM）的VHDL代码。

我在两个单独的文件中描述了数据路径和FSM，并在第三个中将它们实例化为VHDL COMPONENT，定义了Fibonacci模块。使用Quartus II软件，“分析与综合”成功，没有错误和非常恼人的警告“警告（13024）：输出引脚卡在VCC或GND”。是什么让这个警告真正令人烦恼的是，它显示了Fibonacci模块最关键的输出，这是它的最终结果。此输出在我的代码中称为“d_o”。

“data_o”输出引脚来自数据路径组件，也使用加法器，减法器，寄存器和多路复用器等COMPONENT进行描述。单独编译（Analysis＆amp; Sysnthesis）数据路径时，警告会再次显示相同的输出。

我真的不知道我的代码有什么问题，希望你们能帮助我。代码如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL; 
USE IEEE.NUMERIC_STD.ALL;

ENTITY datapath IS
GENERIC (NUMBITS    : NATURAL := 32);
PORT (  SIGNAL rst          : IN STD_LOGIC;
        SIGNAL clk          : IN STD_LOGIC;

        ---Sinal de entrada---
        SIGNAL data_in      : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);

        ---Sinais de seleção---
        SIGNAL di_sel       : IN STD_LOGIC;
        SIGNAL nf_sel       : IN STD_LOGIC;
        SIGNAL na1_sel      : IN STD_LOGIC;
        SIGNAL na2_sel      : IN STD_LOGIC;
        SIGNAL io_sel       : IN STD_LOGIC;
        SIGNAL so0_sel      : IN STD_LOGIC;
        SIGNAL so1_sel      : IN STD_LOGIC;

        ---Sinais load---
        SIGNAL nf_ld        : IN STD_LOGIC;
        SIGNAL di_ld        : IN STD_LOGIC;
        SIGNAL na1_ld       : IN STD_LOGIC;
        SIGNAL na2_ld       : IN STD_LOGIC;
        SIGNAL do_ld        : IN STD_LOGIC;

        ---Sinais das comparações---
        SIGNAL di_eq_0      : OUT STD_LOGIC;
        SIGNAL di_eq_1      : OUT STD_LOGIC;

        ---Sinais de saída---
        SIGNAL irq_o        : OUT STD_LOGIC;
        SIGNAL status_o     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
        SIGNAL d_o          : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END datapath;


ARCHITECTURE behavior OF datapath IS
---Componentes do datapath---   
COMPONENT somador
    GENERIC (NUMBITS    : NATURAL := 32);
    PORT (  SIGNAL x    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL y    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL XY   : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;

COMPONENT subtrator
    GENERIC (NUMBITS    : NATURAL := 32);
    PORT (  SIGNAL x    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL y    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL XY   : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;

COMPONENT reg
    GENERIC (NUMBITS    : NATURAL := 32);
    PORT( SIGNAL rst    : IN STD_LOGIC;
          SIGNAL clk    : IN STD_LOGIC;
          SIGNAL load   : IN STD_LOGIC;
          SIGNAL d      : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
          SIGNAL q      : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;

COMPONENT multiplexor2a1
    GENERIC (NUMBITS    : NATURAL := 32);
    PORT (  SIGNAL a    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL b    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL sel  : IN STD_LOGIC;
            SIGNAL f    : OUT STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0));
END COMPONENT;

COMPONENT igual
    GENERIC (NUMBITS    : NATURAL := 32);
    PORT (  SIGNAL a    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL b    : IN STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
            SIGNAL eq   : OUT STD_LOGIC);
END COMPONENT;

---Sinais de conexão---
SIGNAL mux2di           : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2nf           : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2na1          : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL mux2na2          : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);

---Saidas dos registradores---  
SIGNAL nf_o             : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL di_o             : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL na1_o            : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL na2_o            : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);

---Saidas do somador e do subtrator---
SIGNAL a_result         : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL s_result         : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);

---Constatntes---   
SIGNAL one              : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);
SIGNAL zero             : STD_LOGIC_VECTOR(NUMBITS-1 DOWNTO 0);

BEGIN
zero <= "00000000000000000000000000000000";
one  <= "00000000000000000000000000000001";

---Lógica para irq_o---
WITH io_sel SELECT
    irq_o <= '0' WHEN '0', '1' WHEN OTHERS;

---Lógica para status_o---
WITH so0_sel SELECT
    status_o(0) <= '0' WHEN '0', '1' WHEN OTHERS;
WITH so1_sel SELECT
    status_o(1) <= '0' WHEN '0', '1' WHEN OTHERS;

---Multiplexadores(4)---
mux1: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (data_in, s_result, di_sel, mux2di);
mux2: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (one, nf_o, nf_sel, mux2nf);
mux3: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (zero, na1_o, na1_sel, mux2na1);
mux4: multiplexor2a1 GENERIC MAP(NUMBITS) PORT MAP (a_result, di_o, na2_sel, mux2na2);

---Registradores(5)---  
d_i: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, di_ld, mux2di, di_o);
na1: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, na1_ld, mux2na1, na1_o);
na2: reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, na2_ld, mux2na2, na2_o);
nf:  reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, nf_ld, mux2nf, nf_o);
do:  reg GENERIC MAP (NUMBITS) PORT MAP (rst, clk, do_ld, nf_o, d_o);

---Somador---
a: somador GENERIC MAP(NUMBITS) PORT MAP (na1_o, na2_o, a_result);

---Subtrator---   
s: subtrator GENERIC MAP(NUMBITS) PORT MAP (di_o, one, s_result);

---Comparadores (2)---
eq0:  igual GENERIC MAP(NUMBITS) PORT MAP (di_o, zero, di_eq_0);
eq1:  igual GENERIC MAP(NUMBITS) PORT MAP (di_o, one, di_eq_1);
END ARCHITECTURE;

警告：

"Warning (13024): Output pins are stuck at VCC or GND"

Answer 1

Altera在这个问题上说这个;

Answer 2

显示此错误是因为在模拟过程中您的一个或多个输出永久为高或低。通常，当testbench不考虑所有输出而某些输出被分配了默认值时会出现此问题。如果是这种情况，这不会影响您的设计。

但是，如果给出有效输入的另一个输出被固定为0或1，则应检查代码是否有错误。在这种情况下，还要编辑您的问题，以明确代码需要检查逻辑错误。

VHDL警告“警告（13024）：关键输出上的输出引脚卡在VCC或GND”

2 个答案: