Question

对于课堂，我们制造了一个简单的机器，当输入正确的代码时，该机器应该打开led。无论我以哪种方式进行编码，只要我的代码输入正确，我都会得到相同的奇数错误，即将我的顺序信号全部从on（a0-a4）覆盖为全部ON。它编译没有错误，但是从根本上来说是有问题的。

有人知道为什么吗，我不了解vhdl的基本原理吗？

我将在底部提供其他尝试过的解决方案。

谢谢您的时间

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

entity lab4 is
    Port (
        clk_in: in std_logic;
        switch: in std_logic;
        ledr0, ledr9, ledr8, ledr7, ledr6, ledr5: out std_logic
    );
end lab4;

architecture behavioural of lab4 is

signal a0, a1, a2, a3, a4: std_logic;
signal clk: std_logic;


component DFF_V
   port
   (    clk : in std_logic;
      d : in std_logic;
      q : out std_logic
   );
end component;

component AND_GATE 
    port    (   a,  b, c, d, e  :   in  STD_LOGIC;
    z   :   out STD_LOGIC);
end component;

begin
    D1: DFF_V port map  (clk, switch, a0);
    D2: DFF_V port map  (clk, a0, a1);
    D3: DFF_V port map  (clk, a1, a2);
    D4: DFF_V port map  (clk, a2, a3);
    D5: DFF_V port map  (clk, a3, a4);
    AND1: AND_GATE port map(a0, a1, a2, a3, a4, ledr0);

    clk<= NOT clk_in;

    ledr9 <= a4;
    ledr8 <= a3;
    ledr7 <= a2;
    ledr6 <= a1;
    ledr5 <= a0;


end behavioural;

library IEEE;                       --I modified this code from https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/D_Flip_Flop
use IEEE.STD_LOGIC_1164.ALL;

entity DFF_V is
   port
   (    clk : in std_logic;
      d : in std_logic;
      q : out std_logic
   );
end entity DFF_V;

architecture behavioral of DFF_V is

begin
   process (clk) is
   begin
      if rising_edge(clk) then  
            if (d ='1') then
             q <= '1';
         elsif (d ='0') then 
             q<= '0';       
         end if;
      end if;
   end process;
end architecture behavioral;

牵引电路

项目要求

我已经为a0-a4使用了总线。我试图用if语句在行为上实现我尝试对总线和单独的电线使用case语句我已经分别测试了每段代码，但仍然无法正常工作

为什么我的信号被覆盖，而我的输出却永不亮起？

0 个答案: