Question

从事一个项目，该项目需要我之前编写的自检表测试平台，并且没有问题。

然而，这个错误让我觉得甚至不在那里。错误就在底部，我写了一个箭头指示它的位置。如果有人能够发现我明显无法识别的错误并且知道下次要查找的内容。

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    ENTITY TestBenchAutomated IS

    generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);

    END TestBenchAutomated;

    ARCHITECTURE behavior OF TestBenchAutomated IS 

         -- Component Declaration for the Unit Under Test (UUT)

         COMPONENT TopLevelM_M
         generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
         PORT(
                clk : IN  std_logic;
                next_in : IN  std_logic;
                rst_in : IN  std_logic;
                LEDs : OUT  SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0)
              );
         END COMPONENT;


        --Inputs
        signal clk : std_logic := '0';
        signal next_in : std_logic := '0';
        signal rst_in : std_logic := '0';

        --Outputs
        signal LEDs : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);

        -- Clock period definitions
        constant clk_period : time := 10 ns;

     type Vector is record
            LEDs : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
     end record;

    type VectorArray is array
    (natural range <> ) of Vector;


    constant Vectors : VectorArray := (
    --  LEDs,       
        (X"30"), --48
        (X"f6"),--246
        (X"108"),--264
        (X"FFFFFFD3"),-- -45
        (X"FFFFFF4C"), -- -180
        (X"FFFFFFCF"),-- -49
        (X"ab"), -- 171
        (X"13"), -- 19
        (X"1B"), -- -27
        (X"45"), -- -69
        (X"45"), -- -69
        (X"2d"), -- 45
        (X"122"), -- -290
        (X"56"), -- 86
        (X"f2"), -- 242
        (X"7d"), -- 125
        (X"FFFFFFC9"), -- -55
        (X"115"), -- 277
        (X"FFFFFFE3"), -- -29
        (X"FFFFFF7D")); -- -131


    BEGIN

        -- Instantiate the Unit Under Test (UUT)
        uut: TopLevelM_M PORT MAP (
                 clk => clk,
                 next_in => next_in,
                 rst_in => rst_in,
                 LEDs => LEDs
              );

        -- Clock process definitions
    clk_process :process
    variable  i : integer;
        begin
        for i in Vectors'range loop
            LEDs <= Vectors(i).Test_LEDs;

            wait for clk_period*1;

            wait for 100 ns;
            rst_in <= '1';
            wait for clk_period*3;
            rst_in <= '0';

            for i in 0 to 50 loop --Loops through enough times to cover matrix and more to test what happens

                next_in <= '1';
                wait for clk_period*5;
                next_in <= '0';
                wait for clk_period*1;

                assert LEDs = Vectors(i).Test_LEDs
                report "The answers wrong mate" & integer'image(i)
                severity error;


            end loop;

            wait;

    end process; <------ SAYS THE ERROR IS HERE?!?
END;

感谢您的帮助。

Answer 1

至少在带箭头的end process;之前，您必须添加另一个：

end loop;

合理的缩进可以更容易地发现这样的问题。

但是，这揭示了分配给constant Vectors : VectorArray的另一个问题：

constant Vectors : VectorArray ...中的元素大小不同，因为例如X"30"是8位，其中X"108"是12位。这可以修复通过调整大小。
如果记录只包含一个元素，则无法生成未命名的引用，甚至不在()周围。这是明确说的 VHDL-2002 LRM第7.3.2节聚合：“包含单个聚合的聚合必须始终使用命名关联按顺序指定元素关联将它们与带括号的表达区分开来。“。这可以用使用others或命名参考。

因此声明可能会更新为：

subtype LEDs_t is signed((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);

type Vector is record
  LEDs : LEDs_t;
end record;

type VectorArray is array (natural range <>) of Vector;

constant Vectors : VectorArray := (
  --  LEDs,
  (LEDs => resize(signed'(X"30"), LEDs_t'length)),         --48
  (LEDs => resize(signed'(X"f6"), LEDs_t'length)),         --246
  (LEDs => resize(signed'(X"108"), LEDs_t'length)),        --264
  (LEDs => resize(signed'(X"FFFFFFD3"), LEDs_t'length)),   -- -45
  (LEDs => resize(signed'(X"FFFFFF4C"), LEDs_t'length)),   -- -180
  (LEDs => resize(signed'(X"FFFFFFCF"), LEDs_t'length)),   -- -49
  (LEDs => resize(signed'(X"ab"), LEDs_t'length)),         -- 171
  (LEDs => resize(signed'(X"13"), LEDs_t'length)),         -- 19
  (LEDs => resize(signed'(X"1B"), LEDs_t'length)),         -- -27
  (LEDs => resize(signed'(X"45"), LEDs_t'length)),         -- -69
  (LEDs => resize(signed'(X"45"), LEDs_t'length)),         -- -69
  (LEDs => resize(signed'(X"2d"), LEDs_t'length)),         -- 45
  (LEDs => resize(signed'(X"122"), LEDs_t'length)),        -- -290
  (LEDs => resize(signed'(X"56"), LEDs_t'length)),         -- 86
  (LEDs => resize(signed'(X"f2"), LEDs_t'length)),         -- 242
  (LEDs => resize(signed'(X"7d"), LEDs_t'length)),         -- 125
  (LEDs => resize(signed'(X"FFFFFFC9"), LEDs_t'length)),   -- -55
  (LEDs => resize(signed'(X"115"), LEDs_t'length)),        -- 277
  (LEDs => resize(signed'(X"FFFFFFE3"), LEDs_t'length)),   -- -29
  (LEDs => resize(signed'(X"FFFFFF7D"), LEDs_t'length)));  -- -131

调整大小时不需要显式signed'(...)，因为VHDL将解析在这种情况下使用的正确调整大小，但我认为显式类型指示使意图明确。

作为未成年人，还有一些.Test_LEDs应为.LEDs。

VHDL self checking testbench进程附近的语法错误

1 个答案: