描述： 我正在尝试用4个输入和3个输出写入vhdl模块LUT（查找表）。我希望我的3位输出是一个二进制数，等于输入中的1的数。
我的真相表：
ABCD | XYZ
0000 | 000
0001 | 001
0010 | 001
0011 | 010
0100 | 011
0101 | 010
0110 | 010
0111 | 011
1000个| 001
1001个| 010
1010个| 010
1011个| 011
1100个| 010
1101个| 011
1110个| 011
1111 | 100
我的VHDL代码：
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity lut is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
end lut;
architecture Behavioral of lut is
signal s0: STD_LOGIC;
signal s1: STD_LOGIC;
signal s2: STD_LOGIC;
signal s3: STD_LOGIC;
signal s4: STD_LOGIC;
signal s5: STD_LOGIC;
signal s6: STD_LOGIC;
signal s7: STD_LOGIC;
signal s8: STD_LOGIC;
signal s9: STD_LOGIC;
signal s10: STD_LOGIC;
signal s11: STD_LOGIC;
signal s12: STD_LOGIC;
signal s13: STD_LOGIC;
begin
----------MUX1-----------
process(a,b)
begin
if a='0'
then s0<=a;
else
s0<=b;
end if;
end process;
--------MUX2----------
process(a,b)
begin
if a='0'
then s1<=a;
else
s1<=b;
end if;
end process;
---------MUX3-----------
process(a,b)
begin
if a='0'
then s2<=a;
else
s2<=b;
end if;
end process;
---------MUX4-----------
process(a,b)
begin
if a='0'
then s3<=a;
else
s3<=b;
end if;
end process;
---------MUX5-----------
process(c,d,a)
begin
if a='0'
then s4<=c;
else
s4<=d;
end if;
end process;
---------MUX6-----------
process(c,d,a)
begin
if a='0'
then s5<=c;
else
s5<=d;
end if;
end process;
---------MUX7-----------
process(c,d,a)
begin
if a='0'
then s6<=c;
else
s6<=d;
end if;
end process;
---------MUX8-----------
process(c,d,a)
begin
if a='0'
then s7<=c;
else
s7<=d;
end if;
end process;
---------MUX9-----------
process(s0,s1,b)
begin
if b='0'
then s8<=s0;
else
s8<=s1;
end if;
end process;
---------MUX10-----------
process(s2,s3,b)
begin
if b='0'
then s9<=s2;
else
s9<=s3;
end if;
end process;
---------MUX11-----------
process(s4,s5,b)
begin
if b='0'
then s10<=s4;
else
s10<=s5;
end if;
end process;
---------MUX12-----------
process(s6,s7,b)
begin
if b='0'
then s11<=s6;
else
s11<=s7;
end if;
end process;
---------MUX13-----------
process(s8,s9,c)
begin
if c='0'
then s12<=s8;
x<= s8;
else
s12<=s9;
x<= s9;
end if;
end process;
---------MUX14-----------
process(s10,s11,c)
begin
if c='0'
then s13<=s10;
z<=s10;
else
s13<=s11;
z<=s11
end if;
end process;
---------MUX15-----------
process(s12,s13,d)
begin
if d='0'
then y<=s12;
else
y<=s13;
end if;
end process;
end Behavioral;
假设： 我需要总共15个多路复用器来模拟我需要的东西。它们将级联为一个输出。 我上面总共有15个流程。
问题：
1.）我对多路复用器ABCD的选择是什么？
2.）我是否以正确的方式对此进行建模？我会从给出的信息中实现我想要的吗？
3.）如果有更好的方法或者你有不同的想法，请你提供一个例子吗？
4.）我没有得到我的xyz输出，它接近但我做错了什么？
我试图提供尽可能多的研究。如果您有任何问题，我会立即回复
答案 0 :(得分：4)
除非您只是为了娱乐或学习而在VHDL中愚弄，否则如果您想要LUT，请将其直接写为LUT。可能没有理由将其打包成低级门和多路复用器。相反，只需描述您想要的行为，让VHDL为您完成工作：
例如，这里是您所描述的组合逻辑LUT的简单VHDL：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Number_of_Ones is
port (
--- mapped 3=a, 2=b, 1=c, 0=d
abcd : in std_ulogic_vector(3 downto 0);
-- mapped x=2, y=1, z=0
xyz : out std_ulogic_vector(2 downto 0);
);
end entity;
architecture any of Number_of_Ones is
begin
process (abcd) is
begin
case abcd is
--abcd|xyz
when "0000" => xyz <= "000";
when "0001" => xyz <= "001";
when "0010" => xyz <= "001";
when "0011" => xyz <= "010";
when "0100" => xyz <= "011";
when "0101" => xyz <= "010";
when "0110" => xyz <= "010";
when "0111" => xyz <= "011";
when "1000" => xyz <= "001";
when "1001" => xyz <= "010";
when "1010" => xyz <= "010";
when "1011" => xyz <= "011";
when "1100" => xyz <= "010";
when "1101" => xyz <= "011";
when "1110" => xyz <= "011";
when "1111" => xyz <= "100";
end case;
end process;
end architecture;
正如您所看到的，这正是您复制的真值表，只是修改为符合VHDL语法。你当然可以用几种不同的方式写这个，你可能希望以不同的方式映射端口等，但这应该可以使你走上正确的轨道。
答案 1 :(得分：4)
作为另一个“信任工具”的答案，如果你想计算那些，那就去做吧。你的代码会更清晰，合成器将会非常出色：
process(clk)
variable count : unsigned(xyz'range)
begin
if rising_edge(clk) then
count := (others => '0');
for i in abcd'range loop
if abcd(i) = '1' then
count := count + 1;
end if;
end loop;
xyz <= count;
end if;
end process;
我没有编译或模拟这个，但它应该给你一个想法......当然，为了完整的代码清晰度，你将count / loop方面封装在一个名为count_ones的函数，并从进程中调用它。
答案 2 :(得分：2)
我要在这里走出去告诉你让你的合成器优化它。除此之外，您可以在桌面上使用最小化器（例如espresso），然后使用VHDL对结果进行编码。
我猜这应该是你在瞄准FPGA时应该做的事情：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_count is
port (
a,b,c,d: in std_logic;
x,y,z: out std_logic
);
end entity;
architecture lut of bit_count is
subtype lutin is std_logic_vector (3 downto 0);
subtype lutout is std_logic_vector (2 downto 0);
type lut is array (natural range 0 to 15) of lutout;
constant bitcount: lut := (
"000", "001", "001", "010",
"011", "010", "010", "011",
"001", "010", "010", "011",
"010", "011", "011", "100"
);
signal temp: std_logic_vector (2 downto 0);
begin
temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) );
(x, y, z) <= lutout'(temp(2), temp(1), temp(0));
end architecture;
如果没想到我认为将其优化为ROM可能会在门数方面接近：
-- 0000 0001 0010 0011
-- "000", "001", "001", "010",
-- 0100 0101 0110 0111
-- "011", "010", "010", "011",
-- 1000 1001 1010 1011
-- "001", "010", "010", "011",
-- 1100 1101 1110 1111
-- "010", "011", "011", "100"
-- output Input
-----------------------
-- bit 0 is true 0001 0010 0100 0111 1000 1011 1101 1111
-- bit 1 0011 0100 0101 0110 0111 1001 1010 1011 1100 1101 1110
-- bit 2 1111
architecture rom of bit_count is
signal t0,t1,t2: std_logic;
signal t4,t7,t8: std_logic;
signal t11,t13,t14: std_logic;
signal t15: std_logic;
begin
-- terms
t0 <= not a and not b and not c and not d;
t1 <= a and not b and not c and not d;
t2 <= not a and b and not c and not d;
-- t3 <= a and b and not c and not d;
t4 <= not a and not b and c and not d;
-- t5 <= a and not b and c and not d;
-- t6 <= not a and b and c and not d;
t7 <= a and b and c and not d;
t8 <= not a and not b and not c and d;
-- t9 <= a and not b and not c and d;
-- t10 <= not a and b and not c and d;
t11 <= a and b and not c and d;
-- t12 <= not a and not b and c and d;
t13 <= a and not b and c and d;
t14 <= not a and b and c and d;
t15 <= a and b and c and d;
-- outputs
x <= t15;
y <= not ( t0 or t1 or t2 or t8 or t15 );
Z <= t1 or t2 or t4 or t7 or t8 or t11 or t13 or t14;
end architecture;
它应该比链式多路复用器更少的门，更平坦（更快）。
这两种架构已经过分析但未模拟。在进行手门级编码时很容易出错。