Question

我目前正在使用vhdl并且遇到7段显示问题。我在网上找到了这个代码，但我很难理解它的确切含义。有些人可以通过以下代码帮助我了解正在发生的事情：

ARCHITECTURE Structure OF multi IS
 SIGNAL C : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
 LEDR <= SW;
 C(2 DOWNTO 0) <= SW(2 DOWNTO 0);

 HEX0(0) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(1) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(2) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(3) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(4) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0)) );
 HEX0(5) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(6) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) );
END Structure;

我不理解所有NOT和OR语句中的逻辑。

非常感谢！

Answer 1

当代码从混淆的VHDL竞赛中脱机时，会发生这种情况。

或者更可能是慈善事业，有人将20世纪70年代早期的原理图交给八进制到7段解码器芯片（或电路板！），并要求用VHDL重写它，因为原始组件不再可用。他/她用经典的“产品总和”形式写出来，并没有试图将其最小化......

我相信你能做的最好的事情就是把整个事情写成一个查找表，一点一滴，而不用担心逻辑的细节。

从每个表达开始......

 HEX0(6) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) );

最小化它

 HEX0(6) <= NOT((NOT(C(2)) AND NOT(C(1)));

并为每个值写出来

C  C2  C1  C0  H6  H5  H4  H3  H2  H1  H0   HEX0
0   0   0   0   0   0   0   1   0   0   1   0001001 = 09
1   0   0   1   0
2   0   1   0   1
3   0   1   1   1
4   1   0   0   1
5   1   0   1   1
6   1   1   0   1
7   1   1   1   1

（不完整，也不保证正确......）

然后沿着这些方向重写事物：

subtype Seven_Seg is std_logic_vector(6 downto 0);

constant Lookup : array(0 to 7) of Seven_Seg := ( 0 => "0001001",
                                                  1 => ...
                                                  ...
                                                  7 => ... );

Hex0 <= Lookup(to_integer(unsigned(C)));

并完成它。

7使用VHDL显示段

1 个答案: