Question

所以我正在为7段显示器编写VHDL代码，每秒显示一次（0-F）。我几乎完成了所有事情，我唯一坚持的就是控制器。

我需要有4个按钮，第一个启动计数器，第二个停止，第三个递增一个，最后一个重置为0（我已完成最后一个，我只需要前三个）

这是我的整体代码（注意问题2组件是我的计数器）：

entity SSD is
port (
   seg : out std_logic_vector (6 downto 0);
   an3 : out std_logic;
   btn1, btn2, btn3, btn4 : in std_logic;
   clk : in std_logic);
    end SSD;

    architecture Behavioral of SSD is

    component hex7seg is
    port (
        x : in std_logic_vector (3 downto 0);
        a_to_g : out std_logic_vector (6 downto 0));
    end component;

    component Problem2 is
    port (
        clr : in std_logic;
        ce : in std_logic;
        clk : in std_logic;
        b : out std_logic_vector (3 downto 0);
        tc : out std_logic);
    end component;

component clkdiv is
port (
    rst : in std_logic;
    clk : in std_logic;
    clkout : out std_logic);
end component;

component controller is
port (
    start : in std_logic;
    stop : in std_logic;
    inc : in std_logic;
    rst : in std_logic;
    clk : in std_logic;
    run : out std_logic);
end component;

signal b : std_logic_vector(3 downto 0);
signal run : std_logic;
signal clk_1sec : std_logic;
signal tc : std_logic;

begin

U1: hex7seg port map (x => b, a_to_g => seg);

U2: Problem2 port map (clr=>btn4, ce=>run, clk=>clk_1sec, b=>b, tc=>tc);

U3: controller port map (start => btn1, stop => btn2, inc => btn3, rst => btn4, clk => clk_1sec, run => run);

U4: clkdiv port map (rst => btn4, clk => clk, clkout => clk_1sec);

an3 <= '0';

end Behavioral;

以下是我到目前为止控制器代码的内容：

entity controller is
    Port ( start : in  STD_LOGIC;
           stop : in  STD_LOGIC;
           inc : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           run : out  STD_LOGIC);
end controller;

architecture Behavioral of controller is

begin
    run <= '1';

end Behavioral;

我不确定从哪里开始让其他3个按钮正常工作，我们将非常感谢任何帮助或方向。

Answer 1

您可以添加一个过程来控制“RUN”信号。必须缓冲此信号，因为您不想一直按“START”。对于“INC”，您需要生成一些只能在一个时钟周期内启用计数器的东西。整个事情看起来如下所示：

ctrl: process(clk, rst)
begin
    if rst='1' then
        s_run<='0';
        s_inc<='0';
    elsif rising_edge(clk) then
        -- button controlled RUN signal for counter

        -- stop counter on "stop"
        if stop='1' then
            s_run<='0';

        -- start counter on "start"
        elsif start='1' then
            s_run<='1';     

        -- enable counter for 1 clock on "inc"
        elsif inc='1' and s_inc='0' then
            s_run<='1';

        -- stop counter 1 clock after "inc"!
        elsif s_inc='1' then
            s_run<='0';

        -- otherwise
        else
            s_run<=s_run;
        end if;

        -- buffer of "inc" for edge detection
        s_inc<=inc;
    end if;
end process ctrl;

-- write output
run <= s_run;

请注意，您必须按下按钮至少一个时钟周期......因为您的时钟命名为clk_1sec，这可能是1秒。

VHDL中的7段显示？

1 个答案: