Question

我正在研究vhdl模块。

我想总结6个时钟周期的输入值，然后根据是否达到阈值将输出设置为高电平或低电平。

我遇到的问题是，在最后一个时钟周期，sum值没有加入最终输入值。我需要在时钟的上升沿输出高电平。

以下是代码：

architecture Behavioral of inputCounter is

signal totalBitWidth     : integer := 6;

-- This signal is specified by the user to determine the majority value
-- for the output.
signal majorityValue     : integer := 4;
signal Sum : integer := 0;

process(clk, input)
    variable clkCount     : integer := 0;
begin
    if input = '1' then
        Sum <= Sum + 1;
    else
        Sum <= Sum + 0;
    end if;

    clkCount := clkCount + 1;

    if clkCount >= (totalBitWidth) then
    -- Determine if the majoritySum variable has met the
    -- threshold for a 1 value
    if Sum >= majorityValue then
    output <= '1';
    else
    output <= '0';
    end if;

    if Sum = totalBitWidth Or Sum = 0 then
    countError <= '0';
    else
    countError <= '1';
    end if;

    -- Reset the clock counter, sum value and majority vector
    clkCount := 0;
    Sum <= 0;

    -- Set the bit counter high to alert other midules that a new bit
    -- has been received
    bitReady <= '1';
end process;
end behavioral;

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更新：我正在弄乱整数和我在过程中将其更改为变量而不是体系结构中的整体信号。这似乎有效。但由于我使用的是ISim和ISE Project导航器，因此我无法跟踪该过程中的变量。

Answer 1

解决方法是将我的信号转换为过程中的变量。

这是我的代码：

    architecture Behavioral of inputCounter is

signal totalBitWidth     : integer := 6;

signal majorityValue     : integer := 4;
-- This signal is to trace the variable sum
signal SumS              : integer := 0;



begin

-- Process for recognizing a single input value from a 6 clock cycle
-- wide input signal
majority_proc: process(clk, input)
    variable clkCount     : integer := 0;
    variable Sum  : integer := 0;

    begin

        if rising_edge(clk) And enable = '1' then
            -- Reset bitReady after one clock cycle
            bitReady <= '0';

            -- Check the input value and add it to the Sum variable
            if input = '1' then
                Sum := Sum + 1;
            else
                Sum := Sum + 0;
            end if;

            -- Increment the clock counter variable
            clkCount := clkCount + 1;

            -- Check if the clock count has reached the specified number of cycles
            if clkCount >= totalBitWidth then
                -- Determine if the Sum variable has met the threshold for
                -- value of 1, set the output accordingly
                if Sum >= majorityValue then
                    output <= '1';
                else
                    output <= '0';
                end if;

                -- This checks if the value for all clock cycles was the same and
                -- sets an error flag if not
                if Sum = totalBitWidth Or Sum = 0 then
                    countError <= '0';
                else
                    countError <= '1';
                end if;

                -- Reset the clock counter and sum value
                clkCount := 0;
                Sum := 0;

                -- Set the bit counter high to alert other midules that a new bit
                -- has been received
                bitReady <= '1';
            end if;
        end if;

        -- Assign the variable Sum to the signal SumS
        SumS <= Sum;
end process;

end Behavioral;

Answer 2

如果你必须在同一个时钟周期结束时改变输出，你得到最后一个输入，你需要拆分累加器寄存器和加法器。将累加器寄存器和输出比较逻辑放在您的过程中，并将加法器拉入异步逻辑。缩写示例代码：

process (clk)
  if rising_edge(clk) and enable='1' then
    accumulator <= sum;
    if sum >= majorityValue then
      output <= '1';
    else
      output <= '0';
    end if;
  end if;
end process;

sum <= accumulator + 1 when input='1' else accumulator;

VHDL：计数输入值不记录最终输入

2 个答案: