Question

我想编译这个Verilog代码但我在MultiP模块中的B模块实例中有错误。错误1：未定义的变量B. 错误2：“Adder1”附近：语法错误，意外IDENTIFIER。

代码：

 module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;  
     reg co,sum;

     always @(x | y | ci)
       begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end  
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

  always @(x | y | ci | ppk)
    begin
      A((x & y),ppk,ci,co,ppko);
   end 
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

  always @(x | y )
  begin

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );

  end

endmodule

Answer 1

我想说代码还有其他更微妙的问题。

首先，确保没有声明隐式网络是一种好习惯。否则，拼写错误的网络名称会导致单个网络网络自动创建，结果会出现奇怪的行为

`default_nettype none

然后我建议在模块的端口声明中使用端口网的网络类型声明

module A(input wire x,
     input wire y,
     input wire ci,

     output reg co,
     output reg sum);

   always_comb begin //Use this if you have a system verilog compiler
   always @* begin //Use @* as suggested otherwise 
      sum = x ^ y ^ ci;
      co = (x & y) | (ci & y ) | (ci & x);
   end  
endmodule

module B(input wire ppk,
     input wire x,
     input wire y,
     input wire ci,

     output reg co,
     output reg ppko);

另外，我强烈建议您使用命名参数实例化，如下所示。

   A a(.x(x&y),
       .y(ppk),
       .ci(ci),
       .co(co),
       .ppko(ppko));

endmodule

module MultiP(input wire  [3:0] x,
          input wire  [3:0] y,
          output reg [7:0] ppko);

  wire [12:0] cW;
  wire [12:0] ppW;

   B Adder1(.ppk(x[0]&y[1]),
        .x(y[0]), 
        .y(x[1]), 
        .ci(0), 
        .co(cW[0]), 
        .ppko(ppko[1]));

... //The rest of all B instantiations

endmodule

如前所述，模块实例化并不是在always块中完成的。

我认为你需要阅读一本关于Verilog的好书。我个人从Verilog HDL http://www.amazon.com/Verilog-HDL-paperback-2nd-Edition/dp/0132599708/ref=sr_1_1?ie=UTF8&qid=1362691992&sr=8-1&keywords=verilog+hdl

中学到了什么

Answer 2

我对您的代码进行了少量更改以使其编译：

module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;
     reg co,sum;

     always @* begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

    A A ((x & y),ppk,ci,co,ppko);
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );
endmodule

正如Marty所说，我用*替换了模块A中的始终块敏感性列表。我摆脱了A和B实例周围的总是阻塞。我为A实例添加了一个实例名称。

verilog实例上的错误？

2 个答案: