Question

我正在尝试编写一些vhdl来检测一串位中的给定模式。当电路在输入流中找到模式“110”时，电路应输出1。我的输入是“X”，输出是“Z”。

我不确定如何检查“110”的输入模式。

这是我到目前为止所做的：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity checker is
     Port ( clk : in  STD_LOGIC;
       x : in  STD_LOGIC;
       z : out  STD_LOGIC);
end checker;

architecture Behavioral of checker is

   type state_type is (S0, S1, S2);
   signal pr_state: state_type := S0;
   signal nx_state: state_type := S0;

 begin

process(clk) begin
  if (rising_edge(clk)) then
      pr_state <= nx_state;
  end if;
end process;

process(pr_state, nx_state) begin

case (pr_state) is 

    when S0 =>  
        z <= '0';
        nx_state <= S1;

    when S1 => 
        z <= '0';
        nx_state <= S2;

    when S2 => 
        z <= '1';
        nx_state <= S0;

end case;

end process;

end Behavioral;

有什么想法？感谢您的反馈。

Answer 1

状态机过于复杂（除非有一些要求使用状态逻辑）。使用移位寄存器和比较器是合理的。假设“110”表示'1'是收到的第一位，您可以执行以下操作（警告！我没有测试此代码。）：

architecture Behavioral of checker is
   signal shift_reg : std_logic_vector(2 downto 0) := "000";

begin
  process(clk) begin
      if rising_edge(clk) then

         -- Assert the output signal if the pattern is found
         if (shift_reg = "110") then
            z <= '1';
         else
            z <= '0';
         end if;

         -- Keep a 3-bit deep buffer for comparison.
         shift_reg(2 downto 0) <= shift_reg(1 downto 0) & x;

      end if;
   end process;
end architecture Behavioral;

Answer 2

如果需要FSM，最简单的可能就是探索各种可能性：

achictecture behavior of checker is
   types states is (SEARCHING, SAW_1, SAW_11, SAW_110);
   signal state : states := SEARCHING;

begin
   process (clk) begin
      if rising_edge(clk) then
         case (state) is
         when SEARCHING:
            if (z = '1') then
               state <= SAW_1;
            else
               state <= SEARCHING;
            end if;
            z <= '0';

         when SAW_1:
            if (z = '1') then
               state <= SAW_11;
            else
               state <= SEARCHING;
            end if;
            z <= '0';

         when SAW_11:
            if (z = '0') then
               state <= SAW_110;
            else
               state <= SEARCHING;
            end if;
            z <= '0';

         when SAW_110:
            state <= SEARCHING;
            z <= '1';

         end case;

      end if;
   end process;
end architecture behavior;

这使用与原始代码不同的FSM结构，可以稍微改进一下（至少可以删除1个状态），但我认为这说明了这一点。

VHDL FSM模式检查器

2 个答案: