Question

我想知道是否有人可以阐明如何在verilog中编码led模式fsm，在8个LED上产生4种不同的模式，LED会改变每个滴答脉冲，有4个按钮可触发4种不同的模式，每种模式将触发8个LED以一种模式移动，即从左到右，从右到左。

我已经编写了一个顺序逻辑，但我不知道如何将LED的模式插入每个状态。继承我的代码：

`timescale 1ns / 1ps
module pattern_fsm(
input [3:0] mode,
input tick,
input clk,
input reset,
output reg [7:0] Led
);

 reg [3:0] state, nextstate;

 parameter s0 = 4'b0001;
 parameter s1 = 4'b0010;
 parameter s2 = 4'b0100;
 parameter s3 = 4'b1000;

 always @(posedge clk, posedge reset)
    if(reset) 
        state <= s0;
    else
        state <= nextstate;

always @(*)
    begin
        case(state)
            s0: if(mode == 4'b0001) nextstate = s0;
                    else nextstate = s3;
            s1: if(mode == 4'b0010) nextstate = s1;
                    else nextstate = s0;
            s2: if(mode == 4'b0100) nextstate = s2;
                    else nextstate = s1;
            s3: if(mode == 4'b1000) nextstate = s3;
                    else nextstate = s2;
            default: nextstate = s0;
        endcase
    end

always @(state)
    begin
        case(state)
            s0: Led = 8'b00000001;
            s1: Led = 8'b00000010;
            s2: Led = 8'b00000011;
            s3: Led = 8'b00000100;
        endcase
    end

endmodule

Answer 1

也许你可以使用轮班操作？

always @(posedge clk or posedge reset )
    if(reset) begin
        Led <= 8'h00;
    end
    else begin
        case(state)
            s0: Led <= 8'h01;              // a single Led lit 
            s1: Led <= {Led[0], Led[7:1]}; // rotate right
            s2: Led <= {Led[6:0], Led[7]}; // rotate left
            s3: Led <= ~Led;               // flip?
            default: Led <= Led;           // do nothing
        endcase
    end

我希望你发现这很有启发性。我没有测试过这段代码，所以要小心......

led模式有限状态机verilog

1 个答案: