Question

好的，所以我知道我的代码适用于3数字序列但是对于有限状态机模型我提出这应该是正确的但它不适用于4数字序列。它只检测第一个3.我需要检测序列为01100110110111的重叠“0110”。它应该有3个“0110”序列和2个重叠但是当我运行我的Verilog时它检测到4个“0110”序列告诉我它是只抓“011”有人可以看看我的代码，看看我做错了什么？我可以简单地添加另一个状态，但我不认为这是正确的方法，因为我的图表中没有其他状态。

module moore_seq
(
        input clock, reset, x,
        output reg z
);

//assign binary encoded codes to the states A through D
parameter       A = 2'b00,
                B = 2'b01,
                C = 2'b10,
                D = 2'b11;

reg [1:0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
        casex(current_state) //ignore unknown and Hi-Z inputs
        A:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        B:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        C:      if (x == 1)
                        next_state = D;
                else
                        next_state = B;
        D:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        endcase
end
//Section 2: Output Generator (OG)
always@(*)
begin
        if(current_state == D)
                z = 1;
        else
                z = 0;
end

//Section 3: The Flip Flops
always@(posedge clock, posedge reset)
begin
        if(reset == 1)
                current_state <= A;
        else
                current_state <= next_state;
end
endmodule

更新：

parameter       A = 3'b000,
                B = 3'b001,
                C = 3'b010,
                D = 3'b011,
                E = 3'b100;

reg [1:0] current_state, next_state;

//Section 1: Next state generator (NSG)
always@(*)
begin
        casex(current_state) //ignore unknown and Hi-Z inputs
        A:      if (x == 1)
                        next_state = A;
                else
                        next_state = B;
        B:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        C:      if (x == 1)
                        next_state = D;
                else   
                        next_state = B;
        D:      if (x == 1)
                        next_state = A;
                else
                        next_state = E;
        E:      if (x == 1)
                        next_state = C;
                else
                        next_state = B;
        endcase
end

//Section 2: Output Generator (OG)
always@(*)
begin
        if(current_state == E)
                z = 1;
        else
                z = 0;
end

Answer 1

我想，四个州就足够了。只需改变

//Section 2: Output Generator (OG)
always@(*)
begin
    if(current_state == D)

到

//Section 2: Output Generator (OG)
always@(*)
begin
    if(current_state == D && x == 0 )

有限状态机Verilog 4 num序列

1 个答案: