Question

我想知道如何为滴答计数器编写verilog程序。当快速输入为低电平时，输出标记为高电平，每150 ms一个周期（每7500000个周期） clk期为20ns。如果快速输入为高电平，则每隔一个时钟周期，tick应该高电平一个周期。

我在想我应该计算clk周期，并在满足周期数时使用计数输出tick，但我似乎无法使其工作。

继承我的代码：

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg count;

always @(posedge clk) begin
  count <= count + 1;
  if((fast == 1)&&(count == 2)) begin
    tick <= 1;
  end
  else if(fast == 0)&&(count == 7500000)) begin
    tick <= 1;
  end
end
endmodule

Answer 1

您的计数器只有1位宽，您没有包含重置，您也不需要在计数器归零。 == 2只是= = 7500000的相移。尝试：

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg [22:0] count;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if((fast == 1)&&(count == 2)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else if(fast == 0)&&(count == 7500000)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end
endmodule

或类似以下内容可能会合成较小的内容：

reg  [22:0] count;

wire [22:0] comp = (fast) ? 23'd2: 23'd7500000 ;
wire        done = count >= comp               ;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if(done) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end

Answer 2

更少的门 - 没有比较器 - 只需使用向下计数器：

module tick_counter(  
  input  wire clk,  
  input  wire resetn,  
  input  wire fast,  
  output reg  tick);  

  reg  [22:0] count;  

  wire [22:0] load = (fast) ? 23'd2: 23'd7500000;  
  wire        done = !count;  

  always @(posedge clk or negedge resetn) begin  
    if (!resetn) begin  
      count <= 23'd0;  
      tick  <= 1'b0;  
    end else begin  
      tick  <= 1'b0;  
      count <= count - 23'd1;  
      if(done) begin  
        tick  <= 1'b1;  
        count <= load;  
      end  
    end  
  end  
endmodule//tick_counter

否则，如果您更喜欢向上反转文字。

Tick Counter Verilog

2 个答案: