Question

试图制作一个UART发送器，以将数据从FPGA发送到PC； 9600波特率，8位，无奇偶校验，1个开始和停止位;我用VHDL编写了代码，以我喜欢的方式运行综合并对其进行仿真。我想在BASYS 3 FPGA上看到它，在创建约束后，运行实现发出了一个错误，称为“ Opt_Design错误”。

library ieee;
use ieee.std_logic_1164.all;


entity rs232_omo is
generic(clk_max:integer:=10400); --for baudrate


port(

clk : in std_logic;
rst : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
done : out std_logic;
output : out std_logic;
showstates: out std_logic_vector(3 downto 0)
);
end entity;

architecture dataflow of rs232_omo is

type states is (idle_state,start_state,send_state,stop_state);
signal present_state,next_state : states;
signal data,data_next : std_logic;

begin

process(clk,rst)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin

if rst='1' then
    present_state<=idle_state;
    count:=0;
    data<='1';
    done<='0';

elsif rising_edge(clk) then

    present_state<=next_state;
    count:=count+1;
    index:=index+1;
    data<=data_next;

end if;

end process;

process(present_state,data,clk,rst,start)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin

done<='0';
data_next<='1';

case present_state is

    when idle_state =>
        showstates<="1000";
        data_next<='1';

        if start='1' and rst='0' then
            count:=count+1;
            if count=clk_max then
                next_state<=start_state;
                count:=0;
            end if;    
        end if;

    when start_state =>
        showstates<="0100";
        data_next<='0';

        count:=count+1;
        if count=clk_max then
            next_state<=send_state;
            count:=0;
        end if;

    when send_state =>
        showstates<="0010";
        count:=count+1;
        data_next<=input(index);

        if count=clk_max then
            if index=7 then
                index:=0;
                next_state<=stop_state;
            else
                index:=index+1;
            end if;
        count:=0;
        end if;

    when stop_state =>
        showstates<="0001";
        count:=count+1;
        if count=clk_max then
        next_state<=idle_state;
        done<='1';
        count:=0;
        end if;

   end case;
   end process;
   output<=data;

   end architecture;

这是详细的错误消息

“ [DRC MDRV-1]多个驱动程序网：Net done_OBUF具有多个驱动程序：   done_OBUF_inst_i_1 / O和done_reg / Q“

“在DRC期间发现[Vivado_Tcl 4-78]错误。Opt_Design无法运行。”

此错误的原因是什么？

Answer 1

您在第一个done和第二个process中都分配了done<='0';，这正是实现所抱怨的，不能有多个驱动程序。

从第一个过程中删除{{1}}，它应该完成实施。

（我没有检查其余代码是否完全按照您的要求进行操作。）

尝试运行实现时，Vivado中出现“ Opt_Design错误”

1 个答案: