任何人都可以帮我弄清楚我的VHDL代码有什么问题吗?这是代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg)
begin
segNext <= segReg;
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
end if;
end process;
end Behavioral;
当我尝试合成它/生成编程文件时,我收到了这些警告:
WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
有人可以帮我吗?我一直在看代码,我没有看到任何错误,但显然我做错了。
1)“过程灵敏度列表中缺少以下信号”这可能是Xilinx ISE的错误吗?我不明白为什么我需要第48行的过程敏感性列表中的任何其他信号...
2)“由于其他FF / Latch修整,在块中具有恒定值0”好的,我做错了什么?我根本不想使用锁存器......
3)“信号reset_IBUF没有负载.PAR不会尝试路由此信号。”这是什么意思?我的复位信号有什么问题?为什么不完整?
此代码是我尝试将PS / 2键盘与Spartan 3入门板配合使用。实体“键盘”执行读取并且它正常工作(当我单独测试时,我在dout信号上得到正确的扫描码(我在LED上看到它))。 rx_done是tick(20ns),表示扫描码已成功读取。
所以我只是想知道我是否可以以某种方式识别扫描码(在我的第二个过程中,我正在比较数据信号并将正确的值与segNext信号相比较)并在7段显示器上显示。当我开始工作时,我将实现正确的行为(检测所有扫描代码,检查额外的密钥以及按键和按键事件)。
我不确定我是否需要描述其他内容,如果我这样做,请给我留言:)
感谢您的帮助!!!!
编辑:编辑的代码(将数据添加到敏感度列表,否则添加到if子句):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg, data)
begin
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
else
segNext <= segReg;
end if;
end process;
end Behavioral;
不幸的是,经过这些编辑后,我仍然有这样的警告:
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
答案 0 :(得分:3)
在您的组合过程中,您正在阅读tickDone
,segReg
和data
。灵敏度列表中缺少后者,导致锁存。
另外,请勿使用STD_LOGIC_ARITH或STD_LOGIC_UNSIGNED。它们没有标准化,有几个问题。 http://parallelpoints.com/node/3
答案 1 :(得分:1)
您的第二个过程似乎是尝试使用tickDone作为时钟信号,但您没有正确使用它(即:如果rising_edge(tickDone)或类似),那么您创建的是锁存器而不是触发器(如果tickDone = '1')。使用锁存器,当tickDone为高电平时,输出取决于数据信号的状态,而不在灵敏度列表中。最后,使用敏感列表中的segReg,编写代码的方式,您将segReg异步分配给segNext。
您是否忘记使用cp信号作为时钟在if语句中将所有内容包装在第二个进程中?你所写的内容会更有意义......
答案 2 :(得分:1)
2)“由于其他FF / Latch修整,块中的常量值为0”OK, 我究竟做错了什么 ?我根本不想使用锁存器......
这告诉你这些存储元素是由常量驱动的,而不是它们是锁存器。你有没有模拟过这个?