VHDL:使用输入端口时创建的锁存器

时间:2013-03-22 07:23:29

标签: warnings vhdl synthesize

所以我正在研究合成CPU。

这些是错误:

WARNING:Xst:1710 - FF/Latch <EXS/mem_address_0> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_1> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_2> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_3> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process.

然后从这里级联到其他一些东西。

这是给我一个错误的零件组件:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity EX_stage is
    Port(   clk : in  STD_LOGIC;
        rst : in  STD_LOGIC;
        mem_opr_in : in  STD_LOGIC_VECTOR (1 downto 0);
        wb_opr_in : in  STD_LOGIC;
        out_opr_in : in  STD_LOGIC;
        alu_mode : in  STD_LOGIC_VECTOR (3 downto 0);
        in1 : in  STD_LOGIC_VECTOR (7 downto 0);
        in2 : in  STD_LOGIC_VECTOR (7 downto 0);
        ra_in : in  STD_LOGIC_VECTOR (1 downto 0);

-- The Ports I'm reading from
        FW_opcode : in  STD_LOGIC_VECTOR (3 downto 0); 
        FW_ra_IN : in  STD_LOGIC_VECTOR (1 downto 0);
        FW_rb_IN : in  STD_LOGIC_VECTOR (1 downto 0);
-- The port I'm writing to
        mem_address : out  STD_LOGIC_VECTOR (7 downto 0);

        mem_opr_out : out  STD_LOGIC_VECTOR (1 downto 0);
        wb_opr_out : out  STD_LOGIC;
        out_opr_out : out  STD_LOGIC;
        alu_result : out  STD_LOGIC_VECTOR (7 downto 0);
        alu_mode_out : out  STD_LOGIC_VECTOR (3 downto 0);
        ra_out : out  STD_LOGIC_VECTOR (1 downto 0);
        z_flag : out  STD_LOGIC;
        n_flag : out  STD_LOGIC);
end EX_stage;

architecture Behavioral of EX_stage is
begin
    process(clk,rst)
        variable temp_result: STD_LOGIC_VECTOR (7 downto 0);
    begin
    -- Not important... I think
    end process;

    process(clk,rst)
    begin
        if rst = '1' then
            mem_address <= (others => '0');
        elsif clk = '1' and clk'event then
            mem_address <= FW_opcode & FW_ra_IN & FW_rb_IN;
            -- If this is <= x"FF"; then it doesn't give the error
        end if;
    end process;
end Behavioral;

在顶级组件中我有:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Top_level_component is
    Port ( portIN : in  STD_LOGIC_VECTOR (7 downto 0);
        portOUT :   out  STD_LOGIC_VECTOR (7 downto 0);
        clk :       in  STD_LOGIC;
        rst :       in  STD_LOGIC);
end Top_level_component;

architecture Behavioral of Top_level_component is

-- Only the offending components shown

    component IF_stage
        port( clk :  in STD_LOGIC;
            rst :    in STD_LOGIC;
            count :  in STD_LOGIC_VECTOR (7 downto 0);
-- All three of these get input to ID_stage AND EX_stage
            opcode : out STD_LOGIC_VECTOR (3 downto 0);
            reg_a :  out STD_LOGIC_VECTOR (1 downto 0);
            reg_b :  out STD_LOGIC_VECTOR (1 downto 0));
    end component;

    component ID_stage is
        port( clk :   in  STD_LOGIC;
            port_IN : in  STD_LOGIC_VECTOR (7 downto 0);
            opcode :  in  STD_LOGIC_VECTOR (3 downto 0);
            ra_IN :   in  STD_LOGIC_VECTOR (1 downto 0);
            rb_IN :   in  STD_LOGIC_VECTOR (1 downto 0);
            zflag :   in  STD_LOGIC;
            nflag :   in  STD_LOGIC;
            RD1_IN :  in  STD_LOGIC_VECTOR (7 downto 0);
            RD2_IN :  in  STD_LOGIC_VECTOR (7 downto 0);
            count :   in STD_LOGIC_VECTOR (7 downto 0);
            previous_opcode : in  STD_LOGIC_VECTOR (3 downto 0);
            MEM_opr : out  STD_LOGIC_VECTOR (1 downto 0);
            WB_opr :  out  STD_LOGIC;
            OUT_opr : out  STD_LOGIC;
            ALU_mode : out  STD_LOGIC_VECTOR (3 downto 0);
            RD1_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
            RD2_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
            ra_OUT :  out  STD_LOGIC_VECTOR (1 downto 0);
            rb_OUT :  out  STD_LOGIC_VECTOR (1 downto 0);
            new_count : out  STD_LOGIC_VECTOR (7 downto 0);
            set_pc :    out  STD_LOGIC);
    end component;

    component EX_stage is
        port( clk :         in  STD_LOGIC;
            rst :       in  STD_LOGIC;
            mem_opr_in : in  STD_LOGIC_VECTOR (1 downto 0);
            wb_opr_in : in  STD_LOGIC;
            out_opr_in : in  STD_LOGIC;
            alu_mode :  in  STD_LOGIC_VECTOR (3 downto 0);
            in1 :       in  STD_LOGIC_VECTOR (7 downto 0);
            in2 :       in  STD_LOGIC_VECTOR (7 downto 0);
            ra_in :         in  STD_LOGIC_VECTOR (1 downto 0);

-- The Offending ports: This is where the signals go in
            FW_opcode : in  STD_LOGIC_VECTOR (3 downto 0);
            FW_ra_IN : in  STD_LOGIC_VECTOR (1 downto 0);
            FW_rb_IN : in  STD_LOGIC_VECTOR (1 downto 0);
            mem_address : out  STD_LOGIC_VECTOR (7 downto 0);
            mem_opr_out : out  STD_LOGIC_VECTOR (1 downto 0);
            wb_opr_out : out  STD_LOGIC;
            out_opr_out : out  STD_LOGIC;
            alu_result : out  STD_LOGIC_VECTOR (7 downto 0);
            alu_mode_out : out  STD_LOGIC_VECTOR (3 downto 0);
            ra_out :    out  STD_LOGIC_VECTOR (1 downto 0);
            z_flag :    out  STD_LOGIC;
            n_flag :    out  STD_LOGIC);
    end component;

    -- Signals used
    signal set_pc   : STD_LOGIC := '0';
    signal new_count : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal count    : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal IF_opcode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal IF_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal IF_reg_b : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal rd_data1 : std_logic_vector(7 downto 0) := (others => '0');
    signal rd_data2 : std_logic_vector(7 downto 0) := (others => '0');

    signal ID_opcode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal ID_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal ID_reg_b : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal ID_data1 : std_logic_vector(7 downto 0) := (others => '0');
    signal ID_data2 : std_logic_vector(7 downto 0) := (others => '0');
    signal ID_mem_opr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal ID_wb_opr : STD_LOGIC := '0';
    signal ID_out_opr : STD_LOGIC := '0';        
    signal EX_data1 : std_logic_vector(7 downto 0) := (others => '0');
    signal EX_data2 : std_logic_vector(7 downto 0) := (others => '0');
    signal EX_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal EX_results : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal EX_alu_mode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
    signal mem_address : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal EX_mem_opr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
    signal EX_wb_opr : STD_LOGIC := '0';
    signal EX_out_opr : STD_LOGIC := '0';
    signal z_flag   : std_logic := '0';
    signal n_flag   : std_logic := '0';

begin

    IFS: IF_stage PORT MAP(
        clk => clk,
        rst => rst,
        count => count,
        opcode => IF_opcode,
        reg_a => IF_reg_a,
        reg_b => IF_reg_b);

    IDS: ID_stage port map(
        clk => clk,
        port_IN => portIN,
        opcode => IF_opcode,
        ra_IN => IF_reg_a,
        rb_IN => IF_reg_b,
        zflag => z_flag,
        nflag => n_flag,
        RD1_IN => rd_data1,
        RD2_IN => rd_data2,
        count => count,
        previous_opcode => EX_alu_mode,
        MEM_opr => ID_mem_opr,
        WB_opr => ID_wb_opr,
        OUT_opr => ID_out_opr,
        ALU_mode => ID_opcode,
        RD1_OUT => ID_data1,
        RD2_OUT => ID_data2,
        ra_OUT => ID_reg_a,
        rb_OUT => ID_reg_b,
        new_count => new_count,
        set_pc => set_pc);

    EXS: EX_stage port map( 
        clk => clk,
        rst => rst,
        mem_opr_in => ID_mem_opr,
        wb_opr_in => ID_wb_opr,
        out_opr_in => ID_out_opr,
        alu_mode => ID_opcode,
        in1 => EX_data1,
        in2 => EX_data2,
        ra_in => ID_reg_a,
        FW_opcode => IF_opcode,
        FW_ra_IN => IF_reg_a,
        FW_rb_IN => IF_reg_b,
        mem_address => mem_address,
        mem_opr_out => EX_mem_opr,
        wb_opr_out => EX_wb_opr,
        out_opr_out => EX_out_opr,
        alu_result => EX_results,
        alu_mode_out => EX_alu_mode,
        ra_out => EX_reg_a,
        z_flag => z_flag,
        n_flag => n_flag);

end Behavioral;

所以在EX_stage中,当使用FW_opcode,FW_ra_IN或FW_rb_IN时,我得到了错误。我不明白。有任何想法吗?我正在尝试将输入合并到输出中吗?

2 个答案:

答案 0 :(得分:2)

这不是错误。这是一个警告,说合成器已检测到信号始终为0,因此可以优化它。 此外,它与标题所示的锁存器无关(请注意,措辞为FF/Latch,只是说信号EXS/mem_address_0是触发器或锁存器。

这不一定是坏事,除非你知道他们也应该能够接受其他价值观。

在这种情况下,我会说好像FW_ra_INFW_rb_IN信号似乎总是0。如果他们应该能够接受其他值,那么请确保它们实际来自正确的地方。

在使用x"FF"替换作业时,您没有收到警告的原因是,您在重置时信号全部为0,而在重置时则为1 - 并且这些位都不是恒定的。

另请查看VHDL synthesis warning FF/Latch has a constant value of 0

答案 1 :(得分:1)

首先,你发布的是警告而不是错误......因此应该是非阻塞的。

然而,警告告诉您,mem_address(3..0)的值始终为“0”。这意味着,FW_ra_IN和FW_rb_IN始终为“0”。这些信号来自您的IF_stage块(IF_reg_a和IF_reg_b)。检查是否在IF_stage内更新这些信号。

另一件事是,在top_level块中没有使用mem_address。因此,在优化过程中可能会被合成器删除。