如何在ISim 12.3上模拟此vhdl代码?我知道它有效,因为我下载到FPGA但我看不到一个好的模拟。
提前感谢,如果它太基本,我很抱歉,但我对此很新。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.packageFlipFlop.all;
use work.packageUtilities.all;
entity contadorFlipFlopD is
Port ( CLK : in STD_LOGIC;
E : in STD_LOGIC;
CLEAR: in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0)
);
end contadorFlipFlopD;
architecture Behavioral of contadorFlipFlopD is
signal dEFFD, dSFFD, aux: std_logic_vector(3 downto 0) := (others=>'0');
--signal CLKslow: std_logic;
begin
aux(0) <= E;
aux(1) <= aux(0) AND dSFFD(0);
aux(2) <= aux(0) AND dSFFD(0);
aux(3) <= aux(0) AND dSFFD(0);
dEFFD(0) <= aux(0) XOR dSFFD(0);
dEFFD(1) <= aux(1) XOR dSFFD(1);
dEFFD(2) <= aux(2) XOR dSFFD(2);
dEFFD(3) <= aux(3) XOR dSFFD(3);
--dF0: divisorFrecuencia PORT MAP(CLK, CLEAR, CLKslow);
ffD0: flipFlopD PORT MAP( dEFFD(0), CLK, dSFFD(0) );
ffD1: flipFlopD PORT MAP( dEFFD(1), CLK, dSFFD(1) );
ffD2: flipFlopD PORT MAP( dEFFD(2), CLK, dSFFD(2) );
ffD3: flipFlopD PORT MAP( dEFFD(3), CLK, dSFFD(3) );
S <= dSFFD;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flipFlopD is
Port ( D, CLK : in STD_LOGIC;
Q : out STD_LOGIC);
end flipFlopD;
architecture a_flipFlopD of flipFlopD is
begin
process (CLK)
begin
if (clk'event AND clk = '1') then
Q <= D;
end if;
end process;
end a_flipFlopD;
这是我的测试平台的样子
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT contadorFlipFlopD
PORT(
CLK : IN std_logic;
E : IN std_logic;
CLEAR : IN std_logic;
S : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal E : std_logic := '1';
signal CLEAR : std_logic := '0';
--Outputs
signal S : std_logic_vector(3 downto 0);
--Signals
signal dEFFD, dSFFD, aux: std_logic_vector(3 downto 0) := "0000";
signal CLKslow: std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: contadorFlipFlopD PORT MAP (
CLK => CLK,
E => E,
CLEAR => CLEAR,
S => S
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;