Question

library IEEE;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SineGen is
    Port (clock             : in  std_logic;
          dac_ab_vpp        : in  integer range 0 to 4095;
          dac_cd_vpp        : in  integer range 0 to 4095;
          sine_dac_ab       : out std_logic_vector(11 downto 0);
          sine_dac_cd       : out std_logic_vector(11 downto 0));
end SineGen;

architecture Behavioral of SineGen is

subtype slv is std_logic_vector(11 downto 0);


begin

        process(clock)
            variable count       : integer range 0 to 255  := 0;
            variable temp_dac_ab : integer range 0 to 4095 := 0;
            variable temp_dac_cd : integer range 0 to 4095 := 0;

        begin   
            if rising_edge(clock) then

我尝试了一切，归结为接下来的两行使输出始终为零，我不明白为什么。它应该是具有正弦函数的输出。（count是每个周期256个样本.n是位数。）以下是有效格式吗？

                -- A*sin (2PI/2^n * count)
                temp_dac_ab := dac_ab_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
                temp_dac_cd := dac_cd_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));

                if count < 256 then 
                    count := count + 1;
                else
                    count := 0;
                end if;

                sine_dac_ab <= conv_std_logic_vector(temp_dac_ab, slv'length); 
                sine_dac_cd <= conv_std_logic_vector(temp_dac_cd, slv'length); 

            end if;


        end process;
end Behavioral;

Answer 1

除了@brianreavis指出的内容之外，您不希望将分数math_2_pi/real(256)转换为整数，因为它总是为0.所以：

temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count) * math_2_pi/real(256))));
temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count) * math_2_pi/real(256))));

Answer 2

我的VHDL让我生气，但我想你想要这个：

temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count * integer(math_2_pi/real(256))))));
temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count * integer(math_2_pi/real(256))))));

（你不想将sin的浮点数舍入/转换，直到你将它与dac_ab_vpp / dac_cd_vpp相乘

我的VHDL正弦函数gen出了什么问题？

2 个答案: