Question

我正在尝试创建一个简单的内存，用于在时钟为1和wrenable为1时存储矢量（同样用于读取），但是不幸的是我一直在面对计时问题：

来源：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test_memdata IS
    PORT (
        address, data : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
        wrenable, clock, rdenable : IN std_logic := '0';
        readout : OUT std_logic_vector(31 DOWNTO 0)
    );
END test_memdata;

ARCHITECTURE arch OF test_memdata IS
    TYPE ram_type IS ARRAY(0 TO 31) OF std_logic_vector(31 DOWNTO 0);
    SIGNAL ram_block : ram_type;
BEGIN
    process(clock, wrenable, address)  
        variable write_addr : integer;
        variable write_en, read_en : std_logic;
    begin
        write_en := wrenable;
        read_en := rdenable;
        write_addr := to_integer(unsigned(address));
        if rising_edge(clock) then
            if write_en = '1' then
                ram_block(write_addr) <= data;
            elsif read_en = '1' then
                readout <= ram_block(write_addr);
            end if;
        end if;
    end process;
END arch;

Modelsim测试平台

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY memdata_test IS
END memdata_test;
ARCHITECTURE arch OF memdata_test IS
    SIGNAL address, data : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
    SIGNAL wrenable, clock, rdenable : std_logic := '0';
    SIGNAL readout : std_logic_vector(31 DOWNTO 0);
    COMPONENT test_memdata IS
        PORT (
            address, data : IN std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
            wrenable, clock, rdenable : IN std_logic := '0';
            readout : OUT std_logic_vector(31 DOWNTO 0)
        );
    END COMPONENT test_memdata;
BEGIN
    uut : test_memdata PORT MAP(
        address => address,
        data => data,
        wrenable => wrenable,
        rdenable => rdenable,
        clock => clock,
        readout => readout
    );

    PROCESS
    BEGIN
        address <= (OTHERS => '0');
        data <= (OTHERS => '1');
        WAIT FOR 200 ns;
        clock <= '1';
        wrenable <= '1';
        WAIT FOR 200 ns;
        clock <= '0';
        wrenable <= '0';
        WAIT FOR 200 ns;
        clock <= '1';
        rdenable <= '1';
        WAIT FOR 200 ns;
        REPORT "end";
        WAIT;
    END PROCESS;
END arch;

在ModelSim中，此测试平台按预期工作：但是在Quartus中，由于某些原因，它无法按预期工作：

但是，如果我在时钟信号上升沿之前扩展rden和wren，它将起作用：

我从事此工作已经很长时间了，非常感谢您对wrenable / rdenable和{ {1}}同时处于上升状态。

谢谢。

ModelSim-Altera 10.1d，Quartus版本13.0sp1

Answer 1

您的内存模型是错误的，您只应使用一个事件（即时钟沿），因此从进程敏感度列表中删除可悲的地址，也不需要3个变量。

祝你好运

汉斯。

读/写具有时钟上升沿和读/写使能信号的向量数组

1 个答案: