Question

抱歉我的英语不好。我想编写一个简单的控制单元或TPG控制器的VHDL代码，它产生一个像S2这样的信号，这个信号来自FSM，它计算时钟的两个上升沿，然后使s2 = 1，所以我想帮助编写一个计数的代码两个上升沿然后产生s2 = 1。然后在第三个周期使其为零。

这是我的代码不起作用：

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY TPG_CONTROL IS
    PORT (   Clock  : IN            STD_LOGIC ;
    TPG_CONTROL_En  : IN            STD_LOGIC ;
    --reset : IN            STD_LOGIC ;
        ST2             : OUT   STD_LOGIC ) ;
END TPG_CONTROL ;

ARCHITECTURE behav OF TPG_CONTROL IS
    SIGNAL Count : std_logic_vector(1 DOWNTO 0) := "00" ;

    TYPE state IS (S0, S1, S2);
SIGNAL Moore_state: state;
SIGNAL Clear: std_logic  ;
begin
U_Moore0: PROCESS (clock, Clear, TPG_CONTROL_En, Count)
BEGIN
    IF(Count = "11") THEN
        Moore_state <= S0;
        Clear <= '1';
    ELSIF ( (rising_edge (clock)) AND TPG_CONTROL_En= '1') THEN 
     -- IF (Count = "11") THEN Clear <= '1' THEN
            IF Clear = '1' THEN
                Count <= "00" ;
            ELSE
                Count <= Count + 1 ;
        --  END IF ;
--  END IF;
--  END IF;  
--  END IF;  

        CASE Moore_state IS
            WHEN S0 =>
              IF Count = "01" THEN
                    Moore_state <= S1; 
               -- ELSE
                 --  Moore_state <= S0;
                END IF;
WHEN S1 =>
              IF Count = "10" THEN 
                                     Moore_state <= S2; 
                           --   ELSE
                             --        Moore_state <= S1; 
                              END IF;
                      WHEN S2 =>
              IF Count = "11" THEN
                                     Moore_state <= S0; 
                               --         ELSE 
                              --       Moore_state <= S1; 
                              END IF;
        END CASE;
    END IF;
    END IF;
    --ST2 <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
 END PROCESS;
U_Moore1: PROCESS (clock, TPG_CONTROL_En)
BEGIN
  IF ( (rising_edge (clock)) AND TPG_CONTROL_En= '1') THEN
    IF ( Moore_state = S2 ) THEN ST2 <= '1' ; 
    ELSE ST2 <= '0' ;
      END IF;
      END IF;

END PROCESS;
END behav ;

Answer 1

修复后面的注释并重新评论：

当时： --ST2＆lt; ='1'当Moore_state = S2 ELSE'0'时; 方法是： - st2＆lt; =＆＃39; 1＆＃39;当moore_state = s2 else＆＃39; 0＆＃39 ;;

您的代码分析和阐述。

编写一个简单的测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity tpg_control_tb is
end entity;

architecture foo of tpg_control_tb is

    signal clk:     std_logic := '0';
    signal enab:    std_logic := '1';
    signal st2:     std_logic;

begin

CLOCK:
    process 
    begin
        wait for 10 ns;
        clk <= not clk;
        if Now > 100 ns then
            wait;
        end if;
    end process;
DUT:
    entity work.tpg_control
    port map (   
        clock => clk,
        tpg_control_en => enab,
        st2 => st2
    );

end architecture;

使用常量tpg_control_en表明您提到的行为，即您没有达到S2。

如果你通过count注释掉异步清除moore_state：

u_moore0: process (clock, clear, tpg_control_en, count)
begin
    if(count = "11") then
        -- moore_state <= s0;
        clear <= '1';
    elsif ( (rising_edge (clock)) and tpg_control_en= '1') then 
     -- if (count = "11") then clear <= '1' then
            if clear = '1' then
                count <= "00" ;
            else
                count <= count + 1 ;
        --  end if ;
--  end if;
--  end if;  
--  end if;  

        case moore_state is
            when s0 =>
              if count = "01" then
                    moore_state <= s1; 
               -- else
                 --  moore_state <= s0;
                end if;
when s1 =>
              if count = "10" then 
                                     moore_state <= s2; 
                           --   else
                             --        moore_state <= s1; 
                              end if;
                      when s2 =>
              if count = "11" then
                                     moore_state <= s0; 
                               --         else 
                              --       moore_state <= s1; 
                              end if;
        end case;
    end if;
    end if;
    -- st2 <= '1' when moore_state = s2 else '0';
 end process;

你真的到了那里：

tpg_control_tb

我怀疑在不知道为什么你有一个异步明确的流程语句敏感性列表可以减少到clock。

因为unsigned / std_logic_vector＆＃34; +＆＃34;翻过来你可以简单地了解你所拥有的东西：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tpg_control is
    port ( 
        clock:          in  std_logic;
        tpg_control_en: in  std_logic;
        --reset:        in  std_logic;
        st2:            out std_logic
    );
end tpg_control;

architecture behav of tpg_control is

    signal count : std_logic_vector(1 downto 0) := "00" ;

    type state is (s0, s1, s2);
    signal moore_state: state;
    -- signal clear: std_logic;

begin

u_moore0: 
    process (clock)
    begin
        -- if(count = "11") then
            -- moore_state <= s0;
            -- clear <= '1';
        -- elsif ...
        if rising_edge(clock) and tpg_control_en = '1' then 

             -- if clear = '1' then
             --     count <= "00" ;
             -- else
            count <= count + 1;

            case moore_state is
                when s0 =>
                    if count = "01" then
                        moore_state <= s1; 
                    end if;
                when s1 =>
                    if count = "10" then 
                        moore_state <= s2; 
                    end if;
                when s2 =>
                    if count = "11" then
                        moore_state <= s0; 
                    end if;
             end case;
             -- end if;
        end if;
     end process;

u_moore1: 
    process (clock)
    begin
        if rising_edge(clock) and tpg_control_en = '1' then
            if  moore_state = s2 then 
                st2 <= '1' ; 
            else st2 <= '0' ;
            end if;
        end if;
    end process;
end behav ;

这显示了州的翻身：

no clear

请注意，count和moore_state以两种不同的类型格式保存相同的信息。你实际上并不需要两者。通常，综合工具能够单独从moore_state生成工作实现。

计数时钟上升沿然后用VHDL中的FSM产生特定信号

1 个答案: