Question

我无法与<>进行部分批量连接。我在Digital Design with Chisel（4.3批量连接）一书中看到了。允许连接两个具有部分匹配信号的束。

我目前正在研究chisel3.2。似乎不起作用，并且在安装它时报告 chisel3.internal.ChiselException: Connection between left (AnonymousBundle(IO io in Fetch)) and source (AnonymousBundle(IO io in Decode)) failed @.regB: Left Record missing field (regB).

此版本是否已更改？

如果更改，我们现在如何进行部分连接？

这是测试代码（不要在意模块，只是保持信号不被优化）：

class Fetch extends Module {
val io = IO(new Bundle {
val instr = Output(UInt(32.W))
val pc = Output(UInt(32.W))
})
  val r = RegInit(0.U(32.W))
  r := r + 1.U
  io.pc := r
  io.instr := r+1.U
}
class Decode extends Module {
val io = IO(new Bundle {
val instr = Input(UInt(32.W))
val pc = Input(UInt(32.W))
val aluOp = Output(UInt(5.W))
val regA = Output(UInt(32.W))
val regB = Output(UInt(32.W))
})
  io.aluOp := io.pc
  io.regA := io.instr
  io.regB := io.instr
}
class Execute extends Module {
val io = IO(new Bundle {
val aluOp = Input(UInt(5.W))
val regA = Input(UInt(32.W))
val regB = Input(UInt(32.W))
val result = Output(UInt(32.W))
})
 io.result := io.regA
  when(io.aluOp > 10.U){
    io.result := io.regB
  }
}

object MAIN{
 def main(args:Array[String]):Unit = {
    Driver.execute(Array(""),()=>new Module{
      val io = IO(new Bundle{
        val result = Output(UInt(32.W))
      })
      val fetch = Module(new Fetch())
      val decode = Module(new Decode())
      val execute = Module(new Execute)
      fetch.io <> decode.io
      decode.io <> execute.io
      io <> execute.io
    })
 }
}

使用“ <>”运算符进行凿子局部批量连接

0 个答案: