Question

考虑以下代码

library ieee;
use ieee.std_logic_1164.all;

package pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
end package;

实体具有以下端口

library ieee;
use ieee.std_logic_1164.all;

entity baz is 
port (iInput : in foo_vector;
      oOutput : out foo_vector);
end;

它由顶层模块实例化。现在的问题是，我如何仅将bar的std_logic_vectors的一部分传递到baz实例中？当我尝试使用（打开）时编译失败

library ieee;
use ieee.std_logic_1164.all;

entity top is 
end;

architecture rtl of top is 
    signal bar: foo_vector (open) (31 downto 0) := (others => (others => '0'));
begin
    inst : entity work.baz 
    port map (iInput => bar(open)(3 downto 0), --The (open) here does not work
              oOutput => open);    
end;

Answer 1

使用带有要部分分配的无约束类型的锯齿状数组使您的生活变得非常困难。我会说：保持简单。只需使用三个单独的数组foovec_A，foovec_B和foovec_C。

但是，如果您确实希望按照自己的方式进行操作，则需要添加逻辑以将所需的信号发送到单独的foo_vector。例如

library ieee;
use ieee.std_logic_1164.all;

package pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
end package;

use work.pkg.all;

entity baz is 
port (iInput : in foo_vector;
      oOutput : out foo_vector);
end;

architecture rtl of baz is begin
end architecture;

entity top is 
end;

library ieee;

architecture rtl of top is 
    use ieee.std_logic_1164.all;
    use work.pkg.all;
    signal bar: foo_vector(open)(31 downto 0) := (others => (others => '0'));
    signal bar_part: foo_vector(open)(3 downto 0);
    signal output : foo_vector(open)(0 downto 0);
begin
    conn : for i in foo generate
        bar_part(i) <= bar(i)(3 downto 0);
    end generate;

    inst : entity work.baz 
    port map (iInput => bar_part,
              oOutput => output);    
end;

将进行编译（VHDL-2008模式）。

VHDL，将std_logic_vector的部分数组传递到实例化的端口映射中

1 个答案: