错误:信号<val <0 >>上单元<模块>中的多源;该信号连接到多个驱动器

时间:2019-11-13 08:18:24

标签: verilog synthesis

在综合上实现时出现此错误:

=========================================================================
* Low Level Synthesis *
=========================================================================

    ERROR:Xst:528 - Multi-source in Unit <Modules> on signal <val<0>>; this signal is connected to multiple drivers.
    Drivers are:
    Primary input port <val<7>>
    Primary input port <val<6>>
    Primary input port <val<5>>
    Primary input port <val<4>>
    Primary input port <val<3>>
    Primary input port <val<2>>
    Primary input port <val<1>>
    Primary input port <val<0>>
    Signal <N1> in Unit <Modules> is assigned to GND


Total REAL time to Xst completion: 23.00 secs
Total CPU time to Xst completion: 23.19 secs

Process "Synthesize - XST" failed

该怎么办才能解决此错误?

我只是使用reg valalways块中分配了固定值50,并且在整个代码中,除了输出声明和实例化。

这是我的代码:

reg val

0 个答案:

没有答案