旋转LED Verilog

时间:2019-11-02 12:18:47

标签: verilog test-bench

我正在尝试为De1-Soc编写代码以制作旋转的led。这是一个从左向右旋转一个LED,从右向左旋转一个LED或停止旋转的系统。旋转方向由输入信号L / R确定。只要接收到停止信号,照明LED就会保持位置变化。 但是我坚持了下去,不能写更多。 这是我的代码

module led_rotate_top_module(clock,reset,lr, led );

input clock, reset,lr, stop;
output [9:0] led;
reg [3:0] next_state;
reg [3:0]current_state;


parameter led1 = 4'b0001;
parameter led2 = 4'b0010;
parameter led3 = 4'b0011;
parameter led4 = 4'b0100;
parameter led5 = 4'b0101;
parameter led6 = 4'b0110;
parameter led7 = 4'b0111;
parameter led8 = 4'b1000;
parameter led9 = 4'b1001;
parameter led10 = 4'b1010;

always @ (posedge clock)
if (reset)
current_state <= led4;
else
current_state <= next_state;


always @ (lr, current_state)
begin
case (current_state)


led1: if (lr)
next_state <= led2;
else 
next_state <= current_state;


led2:if (lr)
next_state <= led3;
else 
next_state <= current_state;


led3:if (lr)
next_state <= led4;
else
next_state <= current_state;


led4:if (lr)
next_state <= led5;
else
next_state <= current_state;


led5:if (lr)
next_state <= led6;
else
next_state <= current_state;


led6:if (lr)
next_state <= led7;
else
next_state <= current_state;

led7:if (lr)
next_state <= led8;
else
next_state <= current_state;

led8:if (lr)
next_state <= led9;
else
next_state <= current_state;

led9:if (lr)
next_state <= led10;
else
next_state <= current_state;

led10:if (lr)
next_state <= led1;
else
next_state <= current_state;

default: next_state <= led4;
endcase
end

我不确定是否应该遵循这种方式?我的意思是我应该用移位寄存器来完成这个项目吗?

0 个答案:

没有答案