我给leds的数组位是[5:0]total，大小为6。我想显示leds的total的二进制值。例如“ 10”->“ 1010”。 LED位置并不重要，只是位需要连续。
七个分段的显示器正在工作，这就是为什么我不认为问题出在约束文件中。
我测试过为led提供一个变量，该变量具有恒定的“ 1”值，并触发了led。
主模块
`timescale 1ns / 1ps
module yemek(
input clk,
input rst,
output [6:0] seg,
output [3:0] an,
output dp,
output reg [5:0]total
);
reg [5:0]musteriler [10:0];
reg [5:0]musteri1 = {1'b0,1'b1,1'b1,1'b1,1'b1,1'b1};
reg [5:0]musteri2 = {1'b1,1'b1,1'b1,1'b1,1'b0,1'b1};
reg [5:0]musteri3 = {1'b1,1'b0,1'b1,1'b0,1'b1,1'b1};
reg [5:0]musteri4 = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b0};
reg [5:0]musteri5 = {1'b1,1'b1,1'b0,1'b1,1'b1,1'b1};
reg [5:0]musteri6 = {1'b0,1'b1,1'b1,1'b1,1'b0,1'b1};
reg [5:0]musteri7 = {1'b1,1'b1,1'b1,1'b0,1'b1,1'b0};
reg [5:0]musteri8 = {1'b0,1'b1,1'b1,1'b1,1'b1,1'b0};
reg [5:0]musteri9 = {1'b0,1'b1,1'b0,1'b1,1'b1,1'b1};
reg [5:0]musteri10 = {1'b0,1'b1,1'b1,1'b1,1'b1,1'b0};
reg [4:0]musteri_no;
reg yarim;
reg musteri_geldi_mi;
wire corba_girdi;
initial begin
musteri_geldi_mi = 1'b1;
musteri_no = 3'd0;
total=5'd0;
yarim=1'b0;
musteriler[0] = 0;
musteriler[1] = musteri1;
musteriler[2] = musteri2;
musteriler[3] = musteri3;
musteriler[4] = musteri4;
musteriler[5] = musteri5;
musteriler[6] = musteri6;
musteriler[7] = musteri7;
musteriler[8] = musteri8;
musteriler[9] = musteri9;
musteriler[10] = musteri10;
end
wire corba_ana_bekle,corba_ana_mus,corba_ana_sonr;
wire tatlisalata_ana_bekle,tatlisalata_ana_mus,tatlisalata_ana_sonr;
wire odeme_kart,odeme_nakit,cikan_total,cikan_n,cikan_k;
wire [5:0]corba_ana_ala,ana_tat_ala,tat_kasa_ala;
or(cikan_total,cikan_n,cikan_k);
always@(cikan_total)begin
if(cikan_n==1'b1)begin
total=total+1;
end
if(cikan_k==1'b1)begin
total=total+1;
end
end
always @ (posedge clk)begin
if(corba_girdi == 1'b0 && musteri_no != 4'd10)begin
if(yarim==1'b1)begin
yarim=1'b0;
musteri_geldi_mi = 1'b1;
musteri_no = musteri_no + 1;
end
else begin
yarim=1'b1;
end
end
else
musteri_geldi_mi = 1'b0;
end
saat saat(.clk(clk),
.rst(rst),
.seg(seg),
.an(an),
.dp(dp)
);
corba corba(.clk(clk),
.girdi(corba_girdi),
.sonraki(corba_ana_sonr),
.musteri(musteri_geldi_mi),
.alacaklar(musteriler[musteri_no]),
.alacak_cikti(corba_ana_ala),
.cikti(corba_ana_mus)
);
ana ana(.clk(clk),
.bekle(tatlisalata_ana_bekle),
.girdi(corba_ana_sonr),
.musteri(corba_ana_mus),
.alacaklar(corba_ana_ala),
.alacak_cikti(ana_tat_ala),
.cikti(tatlisalata_ana_mus)
);
tatli_salata tatli_salata(.clk(clk),
.girdi(tatlisalata_ana_bekle),
.musteri(tatlisalata_ana_mus),
.alacaklar(ana_tat_ala),
.alacak_cikti(tat_kasa_ala),
.kart_bekle(odeme_kart),
.nakit_bekle(odeme_nakit),
.cikti(odeme_mus)
);
odeme odeme(
.musteri(odeme_mus),
.alacaklar(tat_kasa_ala),
.clk(clk),
.cikti_n(cikan_n),
.cikti_k(cikan_k),
.girdi_n(odeme_nakit),
.girdi_k(odeme_kart)
);
endmodule
约束文件
set_property PACKAGE_PIN T18 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN W3 [get_ports {total[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[0]}]
set_property PACKAGE_PIN U3 [get_ports {total[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[1]}]
set_property PACKAGE_PIN P3 [get_ports {total[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[2]}]
set_property PACKAGE_PIN N3 [get_ports {total[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[3]}]
set_property PACKAGE_PIN P1 [get_ports {total[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[4]}]
set_property PACKAGE_PIN L1 [get_ports {total[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {total[5]}]
set_property PACKAGE_PIN W7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN W6 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U8 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V5 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN V7 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.00 -waveform {0 5} [get_ports clk]
我通过仿真测试了输出，total的值增加了clock，最终值为10。但是total的位不会触发led。
如果我将初始值total设置为total的值，则在第一个总是块中将00000设为total。但是，如果我删除了总是阻止的led灯，便可以使用初始值。