Verilog中的32位桶形移位器没有输入

Question

我正在创建具有多个多路复用器的32位移位器，这是代码：

import requests
from bs4 import BeautifulSoup as bs

headers = {
    'User-Agent': 'Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/77.0.3865.120 Safari/537.36',
}

page = 1
with requests.Session() as s:
    s.headers = headers
    while True:
        r = s.get(f'https://techadvisorblog.com/page/{page}/')
        soup = bs(r.content, 'lxml')
        print(soup.select_one('title').text)
        if soup.select_one('[rel=next]') is None:
            break
        page+=1

这是测试台：

module shifter_32bit(a, b, out);
    input [31:0] a;
    input [4:0] b;
    output wire [31:0] out;

    genvar gv_i;
    genvar gv_j;
    genvar step;

    generate
        for (gv_i = 0; gv_i < 5; gv_i = gv_i+1) begin: level
            for(gv_j = 0; gv_j < 32; gv_j = gv_j+1) begin: bit
                wire mux_wire;
                if(gv_i == 0) begin
                    if (gv_j - (1<<gv_i) < 0) begin
                        mux mux_s(b[gv_i], a[gv_i], 1'b0, mux_wire);
                    end else begin
                        mux mux_s(b[gv_i], a[gv_i], a[gv_i - (1<<gv_i)], mux_wire);
                    end
                end else if(gv_i == 4) begin
                    if (gv_j - (1<<gv_i) < 0) begin
                        mux mux_s(b[gv_i], a[gv_i], 1'b0, out[gv_j]);
                    end else begin
                        mux mux_s(b[gv_i], a[gv_i], a[gv_i - (1<<gv_i)], out[gv_j]);
                    end
                end else begin
                    if (gv_j - (1<<gv_i) < 0) begin
                        mux mux_s(b[gv_i], level[gv_i-1].bit[gv_j].mux_wire, 1'b0, mux_wire);
                    end else begin
                        mux mux_s(b[gv_i], level[gv_i-1].bit[gv_j].mux_wire, level[gv_i-1].bit[gv_j - (1<<gv_i)].mux_wire, mux_wire);
                    end
                end
            end
        end
    endgenerate

endmodule //   a[31:0], out[31:0]

但是在仿真中，我注意到移位器中的输入a没有值，在modelim中它显示为'32'hzzzzzzzz'。真的不知道发生了什么。