VHDL波形仿真线/峰值异常

Question

我当前正在构建一个n位减法器，它看起来工作正常，但是我的波形具有这些异常线，这些瞬时线瞬时出现或消失。我不确定是什么原因造成的，而且几天来一直困扰着我。您会看到“负”信号出现尖峰-我怀疑这是由于一些并发问题引起的，但是我尝试搜索各种关键字来找到此问题的根源，但并未提出任何建议：

代码：

一位完整的加法器

library ieee;
use ieee.std_logic_1164.all;

entity one_bit_full_adder is
  port (
    x, y, cin : in std_logic;
    sum, cout: out std_logic);
end one_bit_full_adder;

architecture arch of one_bit_full_adder is
  begin
    sum <= x xor y xor cin;
    cout <= (x and y) or (cin and (x xor y));
  end arch;

N位减法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity n_bit_subtractor is
  generic(constant BIT_LENGTH : integer);
  port (
    a, b : in std_logic_vector(BIT_LENGTH - 1 downto 0);
    negative: out std_logic;
    difference: out std_logic_vector(BIT_LENGTH - 1 downto 0));
end n_bit_subtractor;

architecture arch of n_bit_subtractor is
  component one_bit_full_adder port (x, y, cin: in std_logic; sum, cout: out std_logic); end component;
  signal carry_ins: std_logic_vector(BIT_LENGTH downto 0) := (0 => '1', others => '0');
  signal differences: std_logic_vector(BIT_LENGTH - 1 downto 0);
  signal b_operand: std_logic_vector(BIT_LENGTH - 1 downto 0);

  begin
    b_operand <= not b;
    difference <= differences;
    negative <= differences(BIT_LENGTH - 1) and '1';
    adders: for i in 0 to BIT_LENGTH-1 generate
      H2: one_bit_full_adder port map(x=>a(i), y=>b_operand(i), cin=>carry_ins(i), sum=>differences(i), cout=>carry_ins(i+1));
    end generate;
  end arch;

测试台：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity n_bit_subtractor_test is
end n_bit_subtractor_test;

architecture arch_test of n_bit_subtractor_test is
constant BIT_LEN : integer := 3;
component n_bit_subtractor is
  generic(constant BIT_LENGTH : integer);
  port (
    a, b : in std_logic_vector(BIT_LENGTH - 1 downto 0);
    negative: out std_logic;
    difference: out std_logic_vector(BIT_LENGTH - 1 downto 0));
end component n_bit_subtractor;
signal p0, p1, difference: std_logic_vector(BIT_LEN-1 downto 0) := (others => '0');
signal negative: std_logic;
begin
  uut: n_bit_subtractor
    generic map (BIT_LENGTH => BIT_LEN)
    port map (a => p0, b => p1, difference => difference, negative => negative);

  process
  variable difference_actual: std_logic_vector(BIT_LEN-1 downto 0) := (others => '0');
  begin
    for i in 0 to (2**BIT_LEN)-1 loop
      for k in 0 to (2**BIT_LEN)-1 loop
        wait for 200 ns;
        p1 <= std_logic_vector(unsigned(p1) + 1);
      end loop;
      p0 <= std_logic_vector(unsigned(p0) + 1);
    end loop;

    report "No errors detected. Simulation successful." severity failure;
  end process;

end arch_test;

任何帮助将不胜感激。 ModelSim版本为v10.1d