错误代码full_adder.vhd(18):““”附近:(vcom-1576)需要IDENTIFIER

时间:2019-09-11 14:50:38

标签: modelsim

我有此错误代码

full_adder.vhd(18): near ")": (vcom-1576) expecting IDENTIFIER. 

我尝试了以下操作,但错误仍然出现,有人知道吗?

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;




USE IEEE.numeric_std.ALL;




ENTITY full_adder IS
  PORT (




a_i: in std_logic;



b_i: in std_logic;




c_i: in std_logic;




s_o: out std_logic;




c_o: out std_logic;




);




END full_adder;




ARCHITECTURE calcul OF full_adder IS




signal full_adder: std_logic;




BEGIN



 s_o <= c_i xor a_i xor b_i;




c_o <= c_i and(a_i xor b_i) or (a_i and b_i);



END calcul;

1 个答案:

答案 0 :(得分:0)

端口中的最后一项不应带有“;”。 ';'因为该端口是右括号');'之后的端口。

port (
  a_i: in std_logic;
  ...
  s_o: out std_logic;
  c_o: out std_logic   -- Do not need ';' here 
);                     -- It is here